~ruther/verilog-riscv-semestral-project: testbench/tb_ram.sv 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3

~ruther/verilog-riscv-semestral-project

ref: 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3 verilog-riscv-semestral-project/testbench/tb_ram.sv -rwxr-xr-x 818 bytes

db85fb35 — Rutherther 2 years ago

tests: fix ram and control_unit tests to match newest architecture

0a9a14b7 — Rutherther 2 years ago

test: add ram test