~ruther/verilog-riscv-semestral-project

ref: 308a146292087449ecb82e4b7935f789ab21c64b verilog-riscv-semestral-project/tests/run.py -rwxr-xr-x 6.3 KiB 
tests: add register dump, printing

tests: compile only once, copy proram, memory files to correct locations

feat: add support for official tests

tests: add python test environment for custom tests
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