~ruther/verilog-riscv-semestral-project: testbench/tb_cpu_simple.sv 2f09f768fe5d2888738e473802f708ad6fa8f794

~ruther/verilog-riscv-semestral-project

ref: 2f09f768fe5d2888738e473802f708ad6fa8f794 verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rwxr-xr-x 2.3 KiB

773f4b99 — Rutherther 1 year, 7 months ago

test: add simple cpu test