~ruther/verilog-riscv-semestral-project: testbench/tb_control_unit.sv 2f09f768fe5d2888738e473802f708ad6fa8f794

~ruther/verilog-riscv-semestral-project

ref: 2f09f768fe5d2888738e473802f708ad6fa8f794 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.0 KiB

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches