~ruther/verilog-riscv-semestral-project: testbench/tb_alu.sv 2867e24626f7c4643ffa93cb6ea28f24d3eb2dae

~ruther/verilog-riscv-semestral-project

ref: 2867e24626f7c4643ffa93cb6ea28f24d3eb2dae verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches