~ruther/verilog-riscv-semestral-project

ref: 181e94c4c368df49b63ee435f623436482f2f6a2 verilog-riscv-semestral-project/src/cpu.sv -rwxr-xr-x 3.7 KiB
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
7ad51766 — Rutherther 2 years ago
fix: remove duplicit instruction and pc in cpu
8f631f51 — Rutherther 2 years ago
refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.
82d9e44f — Rutherther 2 years ago
feat: add cpu top level entity