~ruther/verilog-riscv-semestral-project

ref: 0d5d1a1fc04a21df2c7cf81ce969e9c02c125901 verilog-riscv-semestral-project/tests/test_types.py -rwxr-xr-x 928 bytes 
tests: add register dump, printing

feat: add support for official tests
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