~ruther/verilog-riscv-semestral-project

ref: 06261583f05c4889143c9a74e0007ec20034d3d4 verilog-riscv-semestral-project/tests/official/official_tests.py -rwxr-xr-x 1.4 KiB 
tests: add register dump, printing

feat: add support for official tests
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