~ruther/verilog-riscv-semestral-project: testbench/tb_control_unit.sv 02405eecab38bfa1d85e88d908b52a589ee53d30

~ruther/verilog-riscv-semestral-project

ref: 02405eecab38bfa1d85e88d908b52a589ee53d30 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.0 KiB

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches