# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 18:31:58  December 04, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		jesd204b_rx_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC7D6F31I7
set_global_assignment -name TOP_LEVEL_ENTITY jesd204b_link_rx
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:31:58  DECEMBER 04, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH lane_alignment_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME char_alignment -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id char_alignment
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id char_alignment
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME char_alignment_tb -section_id char_alignment
set_global_assignment -name EDA_TEST_BENCH_NAME ilas_parser_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ilas_parser_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id ilas_parser_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ilas_parser_tb -section_id ilas_parser_tb
set_global_assignment -name EDA_TEST_BENCH_NAME link_controller_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id link_controller_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id link_controller_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME link_controller_tb -section_id link_controller_tb
set_global_assignment -name EDA_TEST_BENCH_NAME an8b10bdecoder_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id an8b10bdecoder_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id an8b10bdecoder_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME an8b10bdecoder_tb -section_id an8b10bdecoder_tb
set_global_assignment -name EDA_TEST_BENCH_NAME lane_alignment_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id lane_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id lane_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME lane_alignment_tb -section_id lane_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_NAME frame_alignment_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id frame_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id frame_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME frame_alignment_tb -section_id frame_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id char_alignment
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/char_alignment_tb.vhd -section_id char_alignment
set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/ilas_parser.vhd -section_id ilas_parser_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id ilas_parser_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/ilas_parser_tb.vhd -section_id ilas_parser_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id link_controller_tb
set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/ilas_parser.vhd -section_id link_controller_tb
set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/link_controller.vhd -section_id link_controller_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/link_controller_tb.vhd -section_id link_controller_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id an8b10bdecoder_tb
set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/an8b10b_decoder.vhd -section_id an8b10bdecoder_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/an8b10bdecoder_tb.vhd -section_id an8b10bdecoder_tb
set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/lane_alignment.vhd -section_id lane_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id lane_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/lane_alignment_tb.vhd -section_id lane_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_FILE src/data_link/frame_alignment.vhd -section_id frame_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/functions.vhd -section_id frame_alignment_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/data_link/frame_alignment_tb.vhd -section_id frame_alignment_tb
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE src/synced_combination.vhd
set_global_assignment -name VHDL_FILE src/lmfc_generation.vhd
set_global_assignment -name VHDL_FILE src/lmfc_counter.vhd
set_global_assignment -name VHDL_FILE src/transport/transport_layer.vhd
set_global_assignment -name VHDL_FILE src/jesd204b_pkg.vhd
set_global_assignment -name VHDL_FILE src/jesd204b_link_rx.vhd
set_global_assignment -name VHDL_FILE src/transport/transport_pkg.vhd
set_global_assignment -name VHDL_FILE src/data_link/ring_buffer.vhd
set_global_assignment -name VHDL_FILE testbench/data_link/an8b10bdecoder_tb.vhd
set_global_assignment -name VHDL_FILE src/data_link/an8b10b_decoder.vhd
set_global_assignment -name VHDL_FILE testbench/data_link/link_controller_tb.vhd
set_global_assignment -name VHDL_FILE testbench/data_link/lane_alignment_tb.vhd
set_global_assignment -name VHDL_FILE testbench/data_link/ilas_parser_tb.vhd
set_global_assignment -name VHDL_FILE testbench/data_link/functions.vhd
set_global_assignment -name VHDL_FILE testbench/data_link/frame_alignment_tb.vhd
set_global_assignment -name VHDL_FILE testbench/data_link/char_alignment_tb.vhd
set_global_assignment -name VHDL_FILE src/data_link/link_controller.vhd
set_global_assignment -name VHDL_FILE src/data_link/lane_alignment.vhd
set_global_assignment -name VHDL_FILE src/data_link/ilas_parser.vhd
set_global_assignment -name VHDL_FILE src/data_link/frame_alignment.vhd
set_global_assignment -name VHDL_FILE src/data_link/error_handler.vhd
set_global_assignment -name VHDL_FILE src/data_link/data_link_pkg.vhd
set_global_assignment -name VHDL_FILE src/data_link/data_link_layer.vhd
set_global_assignment -name VHDL_FILE src/data_link/char_alignment.vhd
set_global_assignment -name VHDL_FILE src/descrambler.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top