~ruther/jesd204b-vhdl

ref: b3fc7c64ac7327c0a7e3873dc2bedf16302b067c jesd204b-vhdl/testbench/transport d---------
6d8dae89 — František Boháček 2 years ago
feat: split samples to sample and control bits
e9ed12fe — František Boháček 2 years ago
chore: remove octets_to_sample, put its behavior to transport_layer
cec550fc — Rutherther 2 years ago
Merge pull request #14 from Rutherther/feat/add-frame-clock

Add frame clock handling
222a55a0 — František Boháček 2 years ago
tests: update octets_to_samples tests
bbe8c929 — František Boháček 2 years ago
feat(transport): add testbenches for transport layer

Simple 1 lane CF = 0, 1 lane CF = 1,
multi lane L = 2, CF = 2, M = 4, S = 2 (2 lanes, 2 control words, 4 conventers, 2 samples per frame)