~ruther/jesd204b-vhdl

ref: 35312ab5cee23caaeed2dfb652381af10bc56263 jesd204b-vhdl/testbench/transport d---------
cec550fc — Rutherther 2 years ago
Merge pull request #14 from Rutherther/feat/add-frame-clock

Add frame clock handling
222a55a0 — František Boháček 2 years ago
tests: update octets_to_samples tests
bbe8c929 — František Boháček 2 years ago
feat(transport): add testbenches for transport layer

Simple 1 lane CF = 0, 1 lane CF = 1,
multi lane L = 2, CF = 2, M = 4, S = 2 (2 lanes, 2 control words, 4 conventers, 2 samples per frame)
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