2 files changed, 2 insertions(+), 2 deletions(-)

M Makefile
M testbench/data_link/frame_alignment_tb.vhd

@@ 10,7 10,7 @@ VHDLEX := vhd
 #                 Top level entity                  #
 #                                                   #
 #####################################################
-export TOP_ENTITY := jesd204b_rx
+export TOP_ENTITY := frame_alignment
 export TOP_ENTITY_VHDL := $(SRCDIR)/$(TOP_ENTITY).$(VHDLEX)
 TESTBENCH ?= $(TOP_ENTITY)_tb # default
 

@@ 85,7 85,7 @@ architecture a1 of frame_alignment_tb is
 begin  -- architecture a1
   uut : entity work.frame_alignment
     generic map (
-      SCRAMBLED => false,
+      SCRAMBLING => '0',
       F         => F,
       K         => K)
     port map (