From f7bc2adc13f9a7cf064bd8fcd75d65018e4fabb9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?=
 <fandabohacek@gmail.com>
Date: Sun, 26 Feb 2023 08:12:09 +0100
Subject: [PATCH] chore: update frame alignment tb

---
 Makefile                                   | 2 +-
 testbench/data_link/frame_alignment_tb.vhd | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 90a6f4e..ada88b3 100644
--- a/Makefile
+++ b/Makefile
@@ -10,7 +10,7 @@ VHDLEX := vhd
 #                 Top level entity                  #
 #                                                   #
 #####################################################
-export TOP_ENTITY := jesd204b_rx
+export TOP_ENTITY := frame_alignment
 export TOP_ENTITY_VHDL := $(SRCDIR)/$(TOP_ENTITY).$(VHDLEX)
 TESTBENCH ?= $(TOP_ENTITY)_tb # default
 
diff --git a/testbench/data_link/frame_alignment_tb.vhd b/testbench/data_link/frame_alignment_tb.vhd
index d421dc3..a18ec13 100644
--- a/testbench/data_link/frame_alignment_tb.vhd
+++ b/testbench/data_link/frame_alignment_tb.vhd
@@ -85,7 +85,7 @@ architecture a1 of frame_alignment_tb is
 begin  -- architecture a1
   uut : entity work.frame_alignment
     generic map (
-      SCRAMBLED => false,
+      SCRAMBLING => '0',
       F         => F,
       K         => K)
     port map (
-- 
2.48.1