From c9e57f78a945c1452553708bee8fbfce717cb06f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Sun, 2 Apr 2023 16:56:16 +0200 Subject: [PATCH] fix: correct condition to generate start lanes for subclass 1 --- src/jesd204b_link_rx.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/jesd204b_link_rx.vhd b/src/jesd204b_link_rx.vhd index 075a106..e66b8fa 100644 --- a/src/jesd204b_link_rx.vhd +++ b/src/jesd204b_link_rx.vhd @@ -126,7 +126,7 @@ begin -- architecture a1 data_link_start <= '1' when data_link_ready_vector = all_ones else '0'; end generate start_lanes_subclass_0; - start_lanes_subclass_1: if SUBCLASSV = 0 generate + start_lanes_subclass_1: if SUBCLASSV = 1 generate set_frame_index: process (ci_frame_clk, ci_multiframe_clk, ci_reset) is begin -- process set_frame_idnex if ci_reset = '0' then -- asynchronous reset (active low) -- 2.48.1