~ruther/jesd204b-vhdl: tets: pass ci_multiframe_clk to jesd204b_link_rx

3 files changed, 3 insertions(+), 0 deletions(-)

M testbench/jesd204b_rx_data_tb.vhd
M testbench/jesd204b_rx_ils_tb.vhd
M testbench/jesd204b_rx_kchars_tb.vhd

M testbench/jesd204b_rx_data_tb.vhd => testbench/jesd204b_rx_data_tb.vhd +1 -0

@@ 160,6 160,7 @@ begin  -- architecture a1
     port map (
       ci_char_clk         => char_clk,
       ci_frame_clk        => frame_clk,
+      ci_multiframe_clk   => '0',
       ci_reset            => reset,
       ci_request_sync     => '0',
       di_transceiver_data => di_transceiver_data,

M testbench/jesd204b_rx_ils_tb.vhd => testbench/jesd204b_rx_ils_tb.vhd +1 -0

@@ 156,6 156,7 @@ begin  -- architecture a1
     port map (
       ci_char_clk         => char_clk,
       ci_frame_clk        => frame_clk,
+      ci_multiframe_clk   => '0',
       ci_reset            => reset,
       ci_request_sync     => '0',
       di_transceiver_data => di_transceiver_data,

M testbench/jesd204b_rx_kchars_tb.vhd => testbench/jesd204b_rx_kchars_tb.vhd +1 -0

@@ 96,6 96,7 @@ begin  -- architecture a1
     port map (
       ci_char_clk         => char_clk,
       ci_frame_clk        => frame_clk,
+      ci_multiframe_clk   => '0',
       ci_reset            => reset,
       ci_request_sync     => '0',
       di_transceiver_data => di_transceiver_data,