1 files changed, 0 insertions(+), 24 deletions(-)

D jesd204b_rx_nativelink_simulation.rpt

@@ 1,24 0,0 @@
-Info: Start Nativelink Simulation process
-Info: NativeLink has detected VHDL design -- VHDL simulation models will be used
-
-========= EDA Simulation Settings =====================
-
-Sim Mode              :  RTL
-Family                :  cyclonev
-Quartus root          :  /home/Documents/Linux/intelFPGA/21.1/quartus/linux64/
-Quartus sim root      :  /home/Documents/Linux/intelFPGA/21.1/quartus/eda/sim_lib
-Simulation Tool       :  questa intel fpga
-Simulation Language   :  vhdl
-Version               :  93
-Simulation Mode       :  GUI
-Sim Output File       :  
-Sim SDF file          :  
-Sim dir               :  simulation/modelsim
-
-=======================================================
-
-Info: Starting NativeLink simulation with Questa Intel FPGA software
-Sourced NativeLink script /home/Documents/Linux/intelFPGA/21.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
-Warning: File jesd204b_rx_run_msim_rtl_vhdl.do already exists - backing up current file as jesd204b_rx_run_msim_rtl_vhdl.do.bak11
-Info: Spawning Questa Intel FPGA Simulation software 
-Info: NativeLink simulation flow was successful