From 3124419e0e481dda2719a687b51de00710794087 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Sun, 4 Dec 2022 21:55:08 +0100 Subject: [PATCH] choer: remove device specific simulation config file --- jesd204b_rx_nativelink_simulation.rpt | 24 ------------------------ 1 file changed, 24 deletions(-) delete mode 100644 jesd204b_rx_nativelink_simulation.rpt diff --git a/jesd204b_rx_nativelink_simulation.rpt b/jesd204b_rx_nativelink_simulation.rpt deleted file mode 100644 index dd09c25..0000000 --- a/jesd204b_rx_nativelink_simulation.rpt +++ /dev/null @@ -1,24 +0,0 @@ -Info: Start Nativelink Simulation process -Info: NativeLink has detected VHDL design -- VHDL simulation models will be used - -========= EDA Simulation Settings ===================== - -Sim Mode : RTL -Family : cyclonev -Quartus root : /home/Documents/Linux/intelFPGA/21.1/quartus/linux64/ -Quartus sim root : /home/Documents/Linux/intelFPGA/21.1/quartus/eda/sim_lib -Simulation Tool : questa intel fpga -Simulation Language : vhdl -Version : 93 -Simulation Mode : GUI -Sim Output File : -Sim SDF file : -Sim dir : simulation/modelsim - -======================================================= - -Info: Starting NativeLink simulation with Questa Intel FPGA software -Sourced NativeLink script /home/Documents/Linux/intelFPGA/21.1/quartus/common/tcl/internal/nativelink/modelsim.tcl -Warning: File jesd204b_rx_run_msim_rtl_vhdl.do already exists - backing up current file as jesd204b_rx_run_msim_rtl_vhdl.do.bak11 -Info: Spawning Questa Intel FPGA Simulation software -Info: NativeLink simulation flow was successful -- 2.48.1