From 07a456a23f1e9839c5efd8c0b9505ae57ee8d58b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Sun, 2 Apr 2023 17:50:38 +0200 Subject: [PATCH] tets: pass ci_multiframe_clk to jesd204b_link_rx --- testbench/jesd204b_rx_data_tb.vhd | 1 + testbench/jesd204b_rx_ils_tb.vhd | 1 + testbench/jesd204b_rx_kchars_tb.vhd | 1 + 3 files changed, 3 insertions(+) diff --git a/testbench/jesd204b_rx_data_tb.vhd b/testbench/jesd204b_rx_data_tb.vhd index 6eb176a..eb02f08 100644 --- a/testbench/jesd204b_rx_data_tb.vhd +++ b/testbench/jesd204b_rx_data_tb.vhd @@ -160,6 +160,7 @@ begin -- architecture a1 port map ( ci_char_clk => char_clk, ci_frame_clk => frame_clk, + ci_multiframe_clk => '0', ci_reset => reset, ci_request_sync => '0', di_transceiver_data => di_transceiver_data, diff --git a/testbench/jesd204b_rx_ils_tb.vhd b/testbench/jesd204b_rx_ils_tb.vhd index 0605137..7c824a6 100644 --- a/testbench/jesd204b_rx_ils_tb.vhd +++ b/testbench/jesd204b_rx_ils_tb.vhd @@ -156,6 +156,7 @@ begin -- architecture a1 port map ( ci_char_clk => char_clk, ci_frame_clk => frame_clk, + ci_multiframe_clk => '0', ci_reset => reset, ci_request_sync => '0', di_transceiver_data => di_transceiver_data, diff --git a/testbench/jesd204b_rx_kchars_tb.vhd b/testbench/jesd204b_rx_kchars_tb.vhd index f0cb8c3..980bbd6 100644 --- a/testbench/jesd204b_rx_kchars_tb.vhd +++ b/testbench/jesd204b_rx_kchars_tb.vhd @@ -96,6 +96,7 @@ begin -- architecture a1 port map ( ci_char_clk => char_clk, ci_frame_clk => frame_clk, + ci_multiframe_clk => '0', ci_reset => reset, ci_request_sync => '0', di_transceiver_data => di_transceiver_data, -- 2.48.1