~ruther/jesd204b-vhdl

06ed0558b6ea9a4e6496cbcc2527622db7f02247 — František Boháček 2 years ago 4a807ac
feat: reset everything in ring buffer
1 files changed, 2 insertions(+), 0 deletions(-)

M src/data_link/ring_buffer.vhd
M src/data_link/ring_buffer.vhd => src/data_link/ring_buffer.vhd +2 -0
@@ 45,7 45,9 @@ begin  -- architecture a1
        if ci_reset = '0' then          -- asynchronous reset (active low)
            buff <= (others => '0');
            read_position <= 0;
            write_position <= 0;
            reg_size <= 0;
            co_read_position <= 0;
        elsif ci_clk'event and ci_clk = '1' then  -- rising clock edge
            if ci_read = '1' and size >= READ_SIZE + ci_adjust_position then
                read_position <= (read_position + ci_adjust_position + READ_SIZE) mod BUFFER_SIZE;

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