From 06ed0558b6ea9a4e6496cbcc2527622db7f02247 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Sat, 25 Feb 2023 20:57:09 +0100 Subject: [PATCH] feat: reset everything in ring buffer --- src/data_link/ring_buffer.vhd | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/data_link/ring_buffer.vhd b/src/data_link/ring_buffer.vhd index 28ec9ee..7eef4e5 100644 --- a/src/data_link/ring_buffer.vhd +++ b/src/data_link/ring_buffer.vhd @@ -45,7 +45,9 @@ begin -- architecture a1 if ci_reset = '0' then -- asynchronous reset (active low) buff <= (others => '0'); read_position <= 0; + write_position <= 0; reg_size <= 0; + co_read_position <= 0; elsif ci_clk'event and ci_clk = '1' then -- rising clock edge if ci_read = '1' and size >= READ_SIZE + ci_adjust_position then read_position <= (read_position + ci_adjust_position + READ_SIZE) mod BUFFER_SIZE; -- 2.48.1