~ruther/avr-device

4e1e8d21aa0dba971d677c85bb3b0418377422e6 — Rahix 4 years ago 1e0eb40
patch: Restructure timer patches

Redesign timer patch file structure for better modularity.  Now,
`timer/<chip>.yaml` defines all timer peripherals for a chip and uses
peripheral-level includes for patching the actual peripheral.  The
actual peripheral patches live in `timer/dev/<type>.yaml`.

The intermediate `<chip>.yaml` file is needed because peripheral-level
includes are not allowed in top-level files.

Signed-off-by: Rahix <rahix@rahix.de>
7 files changed, 63 insertions(+), 48 deletions(-)

M patch/atmega328p.yaml
M patch/atmega32u4.yaml
M patch/attiny85.yaml
A patch/timer/atmega328p.yaml
A patch/timer/atmega32u4.yaml
A patch/timer/attiny85.yaml
R patch/{common/timer/tc0.yaml => timer/dev/8bit.yaml}
M patch/atmega328p.yaml => patch/atmega328p.yaml +2 -1
@@ 2,7 2,8 @@ _include:
  - "common/ac.yaml"
  - "common/adc.yaml"
  - "common/spi.yaml"
  - "common/timer/tc0.yaml"
  - "common/twi.yaml"
  - "common/usart.yaml"
  - "common/wdt.yaml"

  - "timer/atmega328p.yaml"

M patch/atmega32u4.yaml => patch/atmega32u4.yaml +2 -1
@@ 3,7 3,8 @@ _include:
  - "common/adc.yaml"
  - "common/pll.yaml"
  - "common/spi.yaml"
  - "common/timer/tc0.yaml"
  - "common/twi.yaml"
  - "common/usart.yaml"
  - "common/wdt.yaml"

  - "timer/atmega32u4.yaml"

M patch/attiny85.yaml => patch/attiny85.yaml +2 -1
@@ 1,7 1,8 @@
_include:
  - "common/ac.yaml"
  - "common/wdt.yaml"
  - "common/timer/tc0.yaml"

  - "timer/attiny85.yaml"

USI:
  USICR:

A patch/timer/atmega328p.yaml => patch/timer/atmega328p.yaml +6 -0
@@ 0,0 1,6 @@
# This intermediate file is needed because peripheral-level includes are not
# supported in top-level files.

TC0:
  _include:
    - "dev/8bit.yaml"

A patch/timer/atmega32u4.yaml => patch/timer/atmega32u4.yaml +6 -0
@@ 0,0 1,6 @@
# This intermediate file is needed because peripheral-level includes are not
# supported in top-level files.

TC0:
  _include:
    - "dev/8bit.yaml"

A patch/timer/attiny85.yaml => patch/timer/attiny85.yaml +6 -0
@@ 0,0 1,6 @@
# This intermediate file is needed because peripheral-level includes are not
# supported in top-level files.

TC0:
  _include:
    - "dev/8bit.yaml"

R patch/common/timer/tc0.yaml => patch/timer/dev/8bit.yaml +39 -45
@@ 1,45 1,39 @@
TC0:
  TCCR0A:
    _modify:
      COM0A:
        description: "Compare Output A Mode"
        _write_constraint: enum
      COM0B:
        description: "Compare Output B Mode"
        _write_constraint: enum
      WGM0:
        _write_constraint: enum
    COM0A:
      _replace_enum:
        DISCONNECTED:  [0, "Normal port operation, OC0x disconnected"]
        MATCH_TOGGLE:  [1, "Toggle OC0x on Compare Match (Might depend on WGM)"]
        MATCH_CLEAR:   [2, "Clear OC0x on Compare Match (If PWM is enabled, OC0x is set at TOP)"]
        MATCH_SET:     [3, "Set OC0x on Compare Match (If PWM is enabled, OC0x is cleared at TOP)"]
    COM0B:
      _replace_enum:
        DISCONNECTED:  [0, "Normal port operation, OC0x disconnected"]
        MATCH_TOGGLE:  [1, "Toggle OC0x on Compare Match (Might depend on WGM)"]
        MATCH_CLEAR:   [2, "Clear OC0x on Compare Match (If PWM is enabled, OC0x is set at TOP)"]
        MATCH_SET:     [3, "Set OC0x on Compare Match (If PWM is enabled, OC0x is cleared at TOP)"]
    WGM0:
      _replace_enum:
        NORMAL_TOP:    [0, "Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*"]
        PWM_PHASE:     [1, "Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*"]
        CTC:           [2, "CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*"]
        PWM_FAST:      [3, "Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*"]
  TCCR0B:
    _modify:
      WGM02:
        description: "Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)"
      FOC0*:
        access: write-only
    CS0:
      _replace_enum:
        NO_CLOCK:      [0, "No clock source (Timer/Counter stopped)"]
        DIRECT:        [1, "Running, No Prescaling"]
        PRESCALE_8:    [2, "Running, CLK/8"]
        PRESCALE_64:   [3, "Running, CLK/64"]
        PRESCALE_256:  [4, "Running, CLK/256"]
        PRESCALE_1024: [5, "Running, CLK/1024"]
        EXT_FALLING:   [6, "Running, ExtClk Tx Falling Edge"]
        EXT_RISING:    [7, "Running, ExtClk Tx Rising Edge"]
TCCR?A:
  _modify:
    COM?A:
      description: "Compare Output A Mode"
      _write_constraint: enum
    COM?B:
      description: "Compare Output B Mode"
      _write_constraint: enum
    WGM?:
      _write_constraint: enum
  COM??:
    _replace_enum:
      DISCONNECTED:  [0, "Normal port operation, OCix disconnected"]
      MATCH_TOGGLE:  [1, "Toggle OCix on Compare Match (Might depend on WGM)"]
      MATCH_CLEAR:   [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)"]
      MATCH_SET:     [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)"]
  WGM?:
    _replace_enum:
      NORMAL_TOP:    [0, "Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*"]
      PWM_PHASE:     [1, "Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*"]
      CTC:           [2, "CTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*"]
      PWM_FAST:      [3, "Fast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*"]

TCCR?B:
  _modify:
    WGM?2:
      description: "Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes)"
    FOC??:
      access: write-only
  CS?:
    _replace_enum:
      NO_CLOCK:      [0, "No clock source (Timer/Counter stopped)"]
      DIRECT:        [1, "Running, No Prescaling"]
      PRESCALE_8:    [2, "Running, CLK/8"]
      PRESCALE_64:   [3, "Running, CLK/64"]
      PRESCALE_256:  [4, "Running, CLK/256"]
      PRESCALE_1024: [5, "Running, CLK/1024"]
      EXT_FALLING:   [6, "Running, ExtClk Tx Falling Edge"]
      EXT_RISING:    [7, "Running, ExtClk Tx Rising Edge"]

Do not follow this link