library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is

  port (
    clk_i   : in  std_logic;
    rst_in  : in  std_logic;
    count_o : out std_logic_vector(9 downto 0);
    led_o   : out std_logic);

end entity counter;

architecture a1 of counter is
  signal curr_count : unsigned(9 downto 0);
  signal next_count : unsigned(9 downto 0);
begin  -- architecture a1

  set_count: process (clk_i) is
  begin  -- process set_count
    if rising_edge(clk_i) then          -- rising clock edge
      if rst_in = '0' then              -- synchronous reset (active low)
        curr_count <= (others => '0');
      else
        curr_count <= next_count;
      end if;
    end if;
  end process set_count;

  next_count <= curr_count + 1 when curr_count /= "1111111111" else
                (others => '0');

  count_o <= std_logic_vector(curr_count);
  led_o <= curr_count(9);

end architecture a1;