From d5153eaa1015187bf76a1c9607726bdf221634c6 Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@protonmail.com>
Date: Tue, 8 Oct 2024 21:01:25 +0200
Subject: [PATCH] feat: add example vhd, testbench

---
 src/example.vhd          | 54 ++++++++++++++++++++++++++++++++++++
 testbench/example_tb.vhd | 60 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 114 insertions(+)
 create mode 100644 src/example.vhd
 create mode 100644 testbench/example_tb.vhd

diff --git a/src/example.vhd b/src/example.vhd
new file mode 100644
index 0000000..551b776
--- /dev/null
+++ b/src/example.vhd
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity example is
+
+  port (
+    rst_in : in  std_logic;
+    clk_i  : in  std_logic;
+    btn_i  : in  std_logic;
+    led_o  : out std_logic);
+
+end entity example;
+
+architecture a1 of example is
+  signal curr_counter : integer range 0 to 10;
+  signal next_counter : integer range 0 to 10;
+
+  signal curr_counter_en : std_logic;
+  signal next_counter_en : std_logic;
+begin  -- architecture a1
+
+  counter: process (clk_i) is
+  begin  -- process counter
+    if rising_edge(clk_i) then          -- rising clock edge
+      if rst_in = '0' then              -- synchronous reset (active low)
+        curr_counter <= 0;
+      else
+        curr_counter <= next_counter;
+      end if;
+    end if;
+  end process counter;
+
+  counter_en: process (clk_i) is
+  begin  -- process counter_en
+    if rising_edge(clk_i) then          -- rising clock edge
+      if rst_in = '0' then              -- synchronous reset (active low)
+        curr_counter_en <= '0';
+      else
+        curr_counter_en <= next_counter_en;
+      end if;
+    end if;
+  end process counter_en;
+
+  next_counter_en <= '1' when curr_counter_en = '1' and next_counter /= 0 else
+                     '1' when btn_i = '1' else
+                     '0';
+
+  next_counter <= 0 when curr_counter_en = '0' else
+                  curr_counter + 1 when curr_counter < curr_counter'high else
+                  0;
+
+  led_o <= '1' when curr_counter /= 0 else '0';
+
+end architecture a1;
diff --git a/testbench/example_tb.vhd b/testbench/example_tb.vhd
new file mode 100644
index 0000000..fab0a13
--- /dev/null
+++ b/testbench/example_tb.vhd
@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library PROJECT;
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+entity example_tb is
+  generic (
+    runner_cfg : string);
+end entity example_tb;
+
+architecture behav of example_tb is
+  signal clk : std_logic := '0';
+  constant CLK_PERIOD : time := 10 ns;
+
+  signal rst : std_logic := '0';
+
+  signal led : std_logic := '0';
+  signal btn : std_logic := '0';
+
+begin  -- architecture behav
+
+  clk <= not clk after CLK_PERIOD / 2;
+  rst <= '1' after CLK_PERIOD*2;
+
+  uut: entity PROJECT.example
+    port map (
+      clk_i  => clk,
+      rst_in => rst,
+      btn_i  => btn,
+      led_o  => led);
+
+  main: process is
+  begin  -- process main
+    wait until rst = '1';
+    wait until falling_edge(clk);
+    test_runner_setup(runner, runner_cfg);
+
+    while test_suite loop
+      if run("simple") then
+        btn <= '1';
+        wait until falling_edge(clk);
+        btn <= '0';
+        wait until falling_edge(clk);
+        for i in 0 to 9 loop
+          check_equal(led, '1');
+          wait until falling_edge(clk);
+        end loop;  -- i
+        check_equal(led, '0');
+        wait until falling_edge(clk);
+        check_equal(led, '0');
+      end if;
+    end loop;
+
+    test_runner_cleanup(runner);
+  end process main;
+
+end architecture behav;
-- 
2.48.1