library ieee;
use ieee.std_logic_1164.all;

entity example is

  port (
    rst_in : in  std_logic;
    clk_i  : in  std_logic;
    btn_i  : in  std_logic;
    led_o  : out std_logic);

end entity example;

architecture a1 of example is
  signal curr_counter : integer range 0 to 10;
  signal next_counter : integer range 0 to 10;

  signal curr_counter_en : std_logic;
  signal next_counter_en : std_logic;
begin  -- architecture a1

  counter: process (clk_i) is
  begin  -- process counter
    if rising_edge(clk_i) then          -- rising clock edge
      if rst_in = '0' then              -- synchronous reset (active low)
        curr_counter <= 0;
      else
        curr_counter <= next_counter;
      end if;
    end if;
  end process counter;

  counter_en: process (clk_i) is
  begin  -- process counter_en
    if rising_edge(clk_i) then          -- rising clock edge
      if rst_in = '0' then              -- synchronous reset (active low)
        curr_counter_en <= '0';
      else
        curr_counter_en <= next_counter_en;
      end if;
    end if;
  end process counter_en;

  next_counter_en <= '1' when curr_counter_en = '1' and next_counter /= 0 else
                     '1' when btn_i = '1' else
                     '0';

  next_counter <= 0 when curr_counter_en = '0' else
                  curr_counter + 1 when curr_counter < curr_counter'high else
                  0;

  led_o <= '1' when curr_counter /= 0 else '0';

end architecture a1;