From 6d6f0d480de810a2fe0d2c946ae9c61b6a85c4c6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?=
 <fandabohacek@gmail.com>
Date: Mon, 28 Aug 2023 11:14:32 +0200
Subject: [PATCH] tests: add tests for shift registers

---
 testbench/tb_piso_shift_register.vhd | 75 ++++++++++++++++++++++++++++
 testbench/tb_sipo_shift_register.vhd | 64 ++++++++++++++++++++++++
 2 files changed, 139 insertions(+)
 create mode 100644 testbench/tb_piso_shift_register.vhd
 create mode 100644 testbench/tb_sipo_shift_register.vhd

diff --git a/testbench/tb_piso_shift_register.vhd b/testbench/tb_piso_shift_register.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..12e247015c731fbc36179477b8609e31a0c49fc1
--- /dev/null
+++ b/testbench/tb_piso_shift_register.vhd
@@ -0,0 +1,75 @@
+library spi;
+library ieee;
+use ieee.std_logic_1164.all;
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+entity tb_piso_shift_register is
+  generic (runner_cfg : string);
+end entity;
+
+architecture tb of tb_piso_shift_register is
+  signal data_i : std_logic_vector(7 downto 0);
+  signal store_i : std_logic := '0';
+  signal clk : std_logic := '0';
+  signal q_o : std_logic;
+begin
+  uut: entity spi.piso_shift_register
+    generic map (
+      WIDTH => 8)
+    port map (
+      store_i  => store_i,
+      data_i   => data_i,
+      clk_i  => clk,
+      q_o      => q_o);
+
+  clk <= not clk after 1 ns;
+
+  main: process
+  begin
+    -- test whole shift process
+    test_runner_setup(runner, runner_cfg);
+    show(get_logger(default_checker), display_handler, pass);
+
+    while test_suite loop
+      if run("just_once") then
+        wait until falling_edge(clk);
+        data_i <= "10101010";
+        store_i <= '1';
+        wait until falling_edge(clk);
+        store_i <= '0';
+
+        for i in 0 to 3 loop
+          check_equal(q_o, '1');
+          wait until falling_edge(clk);
+          check_equal(q_o, '0');
+          wait until falling_edge(clk);
+        end loop;  -- i
+      elsif run("reload_in_middle") then
+    -- load some data, read few, load again, read...
+        wait until falling_edge(clk);
+        data_i <= "11001100";
+        store_i <= '1';
+        wait until falling_edge(clk);
+        store_i <= '0';
+        check_equal(q_o, '1');
+        wait until falling_edge(clk);
+        check_equal(q_o, '1');
+        wait until falling_edge(clk);
+        check_equal(q_o, '0');
+        store_i <= '1';
+        data_i <= "11111111";
+
+        for i in 0 to 7 loop
+          wait until falling_edge(clk);
+          store_i <= '0';
+          check_equal(q_o, '1');
+        end loop;  -- i
+      end if;
+    end loop;
+
+    wait until falling_edge(clk);
+    test_runner_cleanup(runner);
+  end process;
+end architecture;
diff --git a/testbench/tb_sipo_shift_register.vhd b/testbench/tb_sipo_shift_register.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..20b5bffe9fd0c5e88c6707a0cefc23a57d5c7855
--- /dev/null
+++ b/testbench/tb_sipo_shift_register.vhd
@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library spi;
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+entity tb_sipo_shift_register is
+
+  generic (
+    runner_cfg : string);
+
+end entity tb_sipo_shift_register;
+
+architecture tb of tb_sipo_shift_register is
+  signal clk : std_logic := '0';
+
+  signal data_i : std_logic := '0';
+  signal q_o : std_logic_vector(7 downto 0);
+begin  -- architecture tb
+  uut: entity spi.sipo_shift_register
+    generic map (
+      WIDTH => 8)
+    port map (
+      clk_i  => clk,
+      data_i =>  data_i,
+      q_o =>  q_o);
+
+  clk <= not clk after 1 ns;
+
+  main: process is
+  begin  -- process main
+    test_runner_setup(runner, runner_cfg);
+    show(get_logger(default_checker), display_handler, pass);
+
+    while test_suite loop
+      if run("just_one") then
+        wait until falling_edge(clk);
+        data_i <= '1';
+        wait until falling_edge(clk);
+        data_i <= '0';
+        for i in 0 to 6 loop
+            wait until falling_edge(clk);
+        end loop;  -- i
+
+        check_equal(q_o, std_logic_vector'("10000000"));
+      elsif run("one zero") then
+        for i in 0 to 3 loop
+            wait until falling_edge(clk);
+            data_i <= '1';
+            wait until falling_edge(clk);
+            data_i <= '0';
+        end loop;  -- i
+
+        wait until falling_edge(clk);
+        check_equal(q_o, std_logic_vector'("10101010"));
+      end if;
+    end loop;
+
+    test_runner_cleanup(runner);
+  end process main;
+
+end architecture tb;