From 6d638ba9f3bd05f274dab1129677a34eceafe4fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Mon, 28 Aug 2023 20:19:43 +0200 Subject: [PATCH] fix: receive data in spi_recv correctly on first clock --- src/spi_recv.vhd | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/spi_recv.vhd b/src/spi_recv.vhd index 2d8f22b44131ddb15c10f248cbf6bb6e8ee004d9..333ab7ae6dfc48a64fca54d4448d269d6602a131 100644 --- a/src/spi_recv.vhd +++ b/src/spi_recv.vhd @@ -16,19 +16,24 @@ end entity spi_recv; architecture a1 of spi_recv is signal bit_index_reg : integer range 0 to WIDTH; + signal bit_index_next : integer range 0 to WIDTH; signal initialized : std_logic; begin -- architecture a1 - recv_o <= '1' when bit_index_reg = 0 and initialized = '1' else + recv_o <= '1' when bit_index_next = 1 and initialized = '1' else '0'; + bit_index_next <= (bit_index_reg + 1) mod WIDTH; + set_bit_index: process (clk_i) is begin -- process set_bit_index if rst_in = '0' then -- synchronous reset (active low) bit_index_reg <= 0; initialized <= '0'; elsif rising_edge(clk_i) then -- rising clock edge - initialized <= '1'; - bit_index_reg <= (bit_index_reg + 1) mod WIDTH; + if initialized = '0' and bit_index_reg = 0 then + initialized <= '1'; + end if; + bit_index_reg <= bit_index_next; end if; end process set_bit_index;