@@ 17,10 17,15 @@ end entity piso_shift_register;
architecture a1 of piso_shift_register is
signal q_reg : std_logic_vector(WIDTH - 1 downto 0);
signal q_next : std_logic_vector(WIDTH - 1 downto 0);
+
+ signal output : std_logic;
+
+ signal data : std_logic_vector(WIDTH - 1 downto 0);
begin -- architecture a1
- q_next <= data_i when store_i = '1' else
- q_reg(WIDTH - 2 downto 0) & '0';
- q_o <= q_reg(WIDTH - 1);
+ data <= data_i when store_i = '1' else q_reg;
+
+ q_next <= data(WIDTH - 2 downto 0) & '0';
+ q_o <= data(WIDTH - 1);
set_q_reg: process (clk_i) is
begin -- process set_q_reg
@@ 31,37 31,45 @@ begin
-- test whole shift process
test_runner_setup(runner, runner_cfg);
show(get_logger(default_checker), display_handler, pass);
+ set_stop_level(failure);
while test_suite loop
if run("just_once") then
wait until falling_edge(clk);
data_i <= "10101010";
store_i <= '1';
+ wait for 0.5 ns;
+ check_equal(q_o, '1');
wait until falling_edge(clk);
store_i <= '0';
- for i in 0 to 3 loop
- check_equal(q_o, '1');
- wait until falling_edge(clk);
+ wait for 0.5 ns;
+ for i in 0 to 2 loop
check_equal(q_o, '0');
wait until falling_edge(clk);
+ check_equal(q_o, '1');
+ wait until falling_edge(clk);
end loop; -- i
elsif run("reload_in_middle") then
-- load some data, read few, load again, read...
wait until falling_edge(clk);
data_i <= "11001100";
store_i <= '1';
+ wait for 0.5 ns;
+ check_equal(q_o, '1');
wait until falling_edge(clk);
store_i <= '0';
check_equal(q_o, '1');
wait until falling_edge(clk);
- check_equal(q_o, '1');
+ check_equal(q_o, '0');
wait until falling_edge(clk);
check_equal(q_o, '0');
store_i <= '1';
data_i <= "11111111";
+ wait for 0.5 ns;
+ check_equal(q_o, '1');
- for i in 0 to 7 loop
+ for i in 0 to 6 loop
wait until falling_edge(clk);
store_i <= '0';
check_equal(q_o, '1');