From b5bfa2ebf2458e67a557e726bea30401e601db87 Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@ditigal.xyz>
Date: Mon, 30 Dec 2024 17:59:11 +0100
Subject: [PATCH] fix: assumptions about synthesizable code
---
hdl_spi/manifest.scm | 2 +
hdl_spi/models/spi_models.py | 1 +
hdl_spi/src/rs_latch.vhd | 12 +-
hdl_spi/src/spi_masterslave.vhd | 186 +++++++++++++-------------
hdl_spi/src/spi_multiplexor.vhd | 63 ---------
hdl_spi/src/spi_peripheral.vhd | 38 ++++--
hdl_spi/tests/Makefile | 2 +-
hdl_spi/tests/test_spi_masterslave.py | 29 ++--
hdl_spi/tests/test_spi_peripheral.py | 5 +-
9 files changed, 146 insertions(+), 192 deletions(-)
delete mode 100644 hdl_spi/src/spi_multiplexor.vhd
diff --git a/hdl_spi/manifest.scm b/hdl_spi/manifest.scm
index 0b674a4..e2f2acf 100644
--- a/hdl_spi/manifest.scm
+++ b/hdl_spi/manifest.scm
@@ -60,6 +60,8 @@ testbenches in Python.")
(list
"python-pytest"
"python"
+ "python-pudb"
+ "python-pytest-pudb"
"vhdl-ls"
"make"
diff --git a/hdl_spi/models/spi_models.py b/hdl_spi/models/spi_models.py
index 3de4f7f..a1680d6 100644
--- a/hdl_spi/models/spi_models.py
+++ b/hdl_spi/models/spi_models.py
@@ -123,6 +123,7 @@ class SpiSlave:
if first != csn_falling:
self._log.error(f"CSN did not fall in time ({max} {unit})!")
+ raise Exception(f"CSN did not fall in time ({max} {unit})!")
continue
# csn fell
diff --git a/hdl_spi/src/rs_latch.vhd b/hdl_spi/src/rs_latch.vhd
index 64fd526..1af8dcd 100644
--- a/hdl_spi/src/rs_latch.vhd
+++ b/hdl_spi/src/rs_latch.vhd
@@ -11,16 +11,20 @@ entity rs_latch is
end entity rs_latch;
architecture a1 of rs_latch is
-
+ signal q : std_logic;
begin -- architecture a1
- data: process (reset_i, set_i) is
+ data: process (all) is
begin -- process data
if set_i = '1' then
- q_o <= '1';
+ q <= '1';
elsif reset_i = '1' then
- q_o <= '0';
+ q <= '0';
+ else
+ q <= q;
end if;
end process data;
+ q_o <= q;
+
end architecture a1;
diff --git a/hdl_spi/src/spi_masterslave.vhd b/hdl_spi/src/spi_masterslave.vhd
index f613321..00257e6 100644
--- a/hdl_spi/src/spi_masterslave.vhd
+++ b/hdl_spi/src/spi_masterslave.vhd
@@ -16,37 +16,45 @@ entity spi_masterslave is
port (
-- IOs
- sck_io : inout std_logic;
- miso_io : inout std_logic;
- mosi_io : inout std_logic;
- csn_io : inout std_logic;
+ sck_i : in std_logic;
+ miso_i : in std_logic;
+ mosi_i : in std_logic;
+ csn_i : in std_logic;
+ sck_o : out std_logic;
+ miso_o : out std_logic;
+ mosi_o : out std_logic;
+ csn_o : out std_logic;
+ sck_t : out std_logic;
+ miso_t : out std_logic;
+ mosi_t : out std_logic;
+ csn_t : out std_logic;
-- Control
- clk_i : in std_logic;
- rst_in : in std_logic;
- en_i : in std_logic;
- master_i : in std_logic;
- clock_polarity_i : in std_logic;
- clock_phase_i : in std_logic;
- size_sel_i : in std_logic_vector(SIZES_2LOG - 1 downto 0);
- div_sel_i : in std_logic_vector(DIVISORS_LOG2 - 1 downto 0);
- pulse_csn_i : in std_logic;
- rx_block_on_full_i : in std_logic;
- lsbfirst_i : in std_logic;
+ clk_i : in std_logic;
+ rst_in : in std_logic;
+ en_i : in std_logic;
+ master_i : in std_logic;
+ clock_polarity_i : in std_logic;
+ clock_phase_i : in std_logic;
+ size_sel_i : in std_logic_vector(SIZES_2LOG - 1 downto 0);
+ div_sel_i : in std_logic_vector(DIVISORS_LOG2 - 1 downto 0);
+ pulse_csn_i : in std_logic;
+ rx_block_on_full_i : in std_logic;
+ lsbfirst_i : in std_logic;
-- Data
-- Rx
- rx_en_i : in std_logic;
- rx_data_o : out std_logic_vector(get_max_natural(SIZES) - 1 downto 0);
- rx_valid_o : out std_logic;
- rx_ready_i : in std_logic;
+ rx_en_i : in std_logic;
+ rx_data_o : out std_logic_vector(get_max_natural(SIZES) - 1 downto 0);
+ rx_valid_o : out std_logic;
+ rx_ready_i : in std_logic;
-- Tx
- tx_en_i : in std_logic;
- tx_data_i : in std_logic_vector(get_max_natural(SIZES) - 1 downto 0);
- tx_valid_i : in std_logic;
- tx_ready_o : out std_logic;
+ tx_en_i : in std_logic;
+ tx_data_i : in std_logic_vector(get_max_natural(SIZES) - 1 downto 0);
+ tx_valid_i : in std_logic;
+ tx_ready_o : out std_logic;
-- State
- busy_o : out std_logic;
- err_lost_rx_data_o : out std_logic;
- clear_lost_rx_data_i : in std_logic);
+ busy_o : out std_logic;
+ err_lost_rx_data_o : out std_logic;
+ clear_lost_rx_data_i : in std_logic);
end entity spi_masterslave;
@@ -106,6 +114,9 @@ architecture a1 of spi_masterslave is
signal master_latch_sample_data : std_logic;
signal master_latch_change_data : std_logic;
+ signal csn, sck, mosi, miso : std_logic;
+ signal csn_en, sck_en, mosi_en, miso_en : std_logic;
+
begin -- architecture a1
master_en <= en_i and master_i;
slave_en <= en_i and not master_i;
@@ -204,8 +215,8 @@ begin -- architecture a1
rst_in => slave_ctrl_rst_n,
clock_polarity_i => clock_polarity_i,
clock_phase_i => clock_phase_i,
- sck_i => sck_io,
- csn_i => csn_io,
+ sck_i => sck_i,
+ csn_i => csn_i,
clock_rising_o => slave_clock_rising,
sample_data_o => slave_latch_sample_data,
change_data_o => slave_latch_change_data);
@@ -243,72 +254,57 @@ begin -- architecture a1
q_o => tx_serial_data,
latch_i => latch_change_data_out);
- master_connection : entity work.spi_multiplexor
- port map (
- en_i => master_en,
- mosi_en_i => master_mosi_en,
- miso_en_i => master_miso_en,
- sck_en_i => master_sck_en,
- csn_en_i => master_csn_en,
- mosi_i => tx_serial_data(0),
- miso_i => '0',
- sck_i => master_sck,
- csn_i => master_csn,
- mosi_o => mosi_io,
- miso_o => miso_io,
- sck_o => sck_io,
- csn_o => csn_io,
- rx_valid_i => master_rx_valid,
- rx_valid_o => rx_valid_o,
- tx_ready_i => master_tx_ready,
- tx_ready_o => tx_ready_o,
- busy_i => master_busy,
- busy_o => busy_o,
- err_lost_rx_data_i => master_err_lost_rx_data,
- err_lost_rx_data_o => err_lost_rx_data_o,
- rst_in => master_ctrl_rst_n,
- rst_on => ctrl_rst_n,
- latch_tx_data_i => master_latch_new_tx_data,
- latch_tx_data_o => latch_new_tx_data,
- latch_sample_data_i => master_latch_sample_data,
- latch_sample_data_o => latch_sample_data,
- latch_change_data_i => master_latch_change_data,
- latch_change_data_o => latch_change_data_out,
- rx_serial_i => miso_io,
- rx_serial_o => rx_serial_data);
-
- slave_connection : entity work.spi_multiplexor
- port map (
- en_i => slave_en,
- mosi_en_i => slave_mosi_en,
- miso_en_i => slave_miso_en,
- sck_en_i => slave_sck_en,
- csn_en_i => slave_csn_en,
- mosi_i => '0',
- miso_i => tx_serial_data(0),
- sck_i => '0',
- csn_i => '0',
- mosi_o => mosi_io,
- miso_o => miso_io,
- sck_o => sck_io,
- csn_o => csn_io,
- rx_valid_i => slave_rx_valid,
- rx_valid_o => rx_valid_o,
- tx_ready_i => slave_tx_ready,
- tx_ready_o => tx_ready_o,
- busy_i => slave_busy,
- busy_o => busy_o,
- err_lost_rx_data_i => slave_err_lost_rx_data,
- err_lost_rx_data_o => err_lost_rx_data_o,
- rst_in => slave_ctrl_rst,
- rst_on => ctrl_rst_n,
- latch_tx_data_i => slave_latch_new_tx_data,
- latch_tx_data_o => latch_new_tx_data,
- latch_sample_data_i => slave_latch_sample_data,
- latch_sample_data_o => latch_sample_data,
- latch_change_data_i => slave_latch_change_data,
- latch_change_data_o => latch_change_data_out,
- rx_serial_i => mosi_io,
- rx_serial_o => rx_serial_data);
+ mosi_t <= slave_mosi_en when slave_en = '1' else
+ master_mosi_en when master_en = '1' else
+ '0';
+ miso_t <= slave_miso_en when slave_en = '1' else
+ master_miso_en when master_en = '1' else
+ '0';
+ sck_t <= slave_sck_en when slave_en = '1' else
+ master_sck_en when master_en = '1' else
+ '0';
+ csn_t <= slave_csn_en when slave_en = '1' else
+ master_csn_en when master_en = '1' else
+ '0';
+
+ mosi_o <= tx_serial_data(0) when master_en = '1' else
+ '0' when slave_en = '1' else
+ '0';
+
+ miso_o <= '0' when master_en = '1' else
+ tx_serial_data(0) when slave_en = '1' else '0';
+
+ sck_o <= master_sck when master_en = '1' else
+ '0';
+
+ csn_o <= master_csn when master_en = '1' else '0';
+
+ rx_valid_o <= master_rx_valid when master_en = '1' else
+ slave_rx_valid when slave_en = '1' else
+ '0';
+ tx_ready_o <= master_tx_ready when master_en = '1' else
+ slave_tx_ready when slave_en = '1' else
+ '0';
+ busy_o <= master_busy when master_en = '1' else
+ slave_busy when slave_en = '1' else
+ '0';
+ err_lost_rx_data_o <= master_err_lost_rx_data when master_en = '1' else
+ slave_err_lost_rx_data when slave_en = '1' else
+ '0';
+ ctrl_rst_n <= master_ctrl_rst_n when master_en = '1' else
+ slave_ctrl_rst_n when slave_en = '1' else
+ '0';
+ latch_new_tx_data <= master_latch_new_tx_data when master_en = '1' else
+ slave_latch_new_tx_data when slave_en = '1' else
+ '0';
+ rx_serial_data <= miso_i when master_en = '1' else
+ mosi_i when slave_en = '1' else
+ '0';
+ latch_sample_data <= master_latch_sample_data when master_en = '1' else
+ slave_latch_sample_data when slave_en = '1' else
+ '0';
+ latch_change_data_out <= master_latch_change_data when master_en = '1' else
+ slave_latch_change_data when slave_en = '1' else
+ '0';
end architecture a1;
diff --git a/hdl_spi/src/spi_multiplexor.vhd b/hdl_spi/src/spi_multiplexor.vhd
deleted file mode 100644
index c2d3a01..0000000
--- a/hdl_spi/src/spi_multiplexor.vhd
+++ /dev/null
@@ -1,63 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity spi_multiplexor is
-
- port (
- en_i : in std_logic;
- mosi_en_i : in std_logic;
- miso_en_i : in std_logic;
- sck_en_i : in std_logic;
- csn_en_i : in std_logic;
- mosi_i : in std_logic;
- miso_i : in std_logic;
- sck_i : in std_logic;
- csn_i : in std_logic;
- mosi_o : out std_logic;
- miso_o : out std_logic;
- sck_o : out std_logic;
- csn_o : out std_logic;
- rx_valid_i : in std_logic;
- rx_valid_o : out std_logic;
- tx_ready_i : in std_logic;
- tx_ready_o : out std_logic;
- busy_i : in std_logic;
- busy_o : out std_logic;
- err_lost_rx_data_i : in std_logic;
- err_lost_rx_data_o : out std_logic;
- rst_in : in std_logic;
- rst_on : out std_logic;
-
- latch_tx_data_i : in std_logic;
- latch_tx_data_o : out std_logic;
-
- latch_sample_data_i : in std_logic;
- latch_sample_data_o : out std_logic;
-
- latch_change_data_i : in std_logic;
- latch_change_data_o : out std_logic;
-
- rx_serial_i : in std_logic;
- rx_serial_o : out std_logic);
-
-end entity spi_multiplexor;
-
-architecture a1 of spi_multiplexor is
-
-begin -- architecture a1
-
- mosi_o <= mosi_i when mosi_en_i = '1' and en_i = '1' else 'Z';
- miso_o <= miso_i when miso_en_i = '1' and en_i = '1' else 'Z';
- sck_o <= sck_i when sck_en_i = '1' and en_i = '1' else'Z';
- csn_o <= csn_i when csn_en_i = '1' and en_i = '1' else'Z';
- rx_valid_o <= rx_valid_i when en_i = '1' else'Z';
- tx_ready_o <= tx_ready_i when en_i = '1' else'Z';
- busy_o <= busy_i when en_i = '1' else'Z';
- err_lost_rx_data_o <= err_lost_rx_data_i when en_i = '1' else'Z';
- rst_on <= rst_in when en_i = '1' else'Z';
- latch_tx_data_o <= latch_tx_data_i when en_i = '1' else'Z';
- latch_sample_data_o <= latch_sample_data_i when en_i = '1' else'Z';
- latch_change_data_o <= latch_change_data_i when en_i = '1' else'Z';
- rx_serial_o <= rx_serial_i when en_i = '1' else 'Z';
-
-end architecture a1;
diff --git a/hdl_spi/src/spi_peripheral.vhd b/hdl_spi/src/spi_peripheral.vhd
index 90e3926..da2a93d 100644
--- a/hdl_spi/src/spi_peripheral.vhd
+++ b/hdl_spi/src/spi_peripheral.vhd
@@ -20,10 +20,18 @@ entity spi_peripheral is
write_i : in std_logic;
read_i : in std_logic;
-- IOs
- sck_io : inout std_logic;
- miso_io : inout std_logic;
- mosi_io : inout std_logic;
- csn_io : inout std_logic;
+ sck_i : in std_logic;
+ miso_i : in std_logic;
+ mosi_i : in std_logic;
+ csn_i : in std_logic;
+ sck_o : out std_logic;
+ miso_o : out std_logic;
+ mosi_o : out std_logic;
+ csn_o : out std_logic;
+ sck_t : out std_logic;
+ miso_t : out std_logic;
+ mosi_t : out std_logic;
+ csn_t : out std_logic;
-- Control
clk_i : in std_logic;
rst_in : in std_logic;
@@ -131,10 +139,18 @@ begin -- architecture a1
CSN_PULSE_CYCLES => CSN_PULSE_CYCLES)
port map (
-- IOs
- sck_io => sck_io,
- miso_io => miso_io,
- mosi_io => mosi_io,
- csn_io => csn_io,
+ sck_o => sck_o,
+ miso_o => miso_o,
+ mosi_o => mosi_o,
+ csn_o => csn_o,
+ sck_i => sck_i,
+ miso_i => miso_i,
+ mosi_i => mosi_i,
+ csn_i => csn_i,
+ sck_t => sck_t,
+ miso_t => miso_t,
+ mosi_t => mosi_t,
+ csn_t => csn_t,
-- Control
clk_i => clk_i,
rst_in => rst_in,
@@ -207,9 +223,9 @@ begin -- architecture a1
case raddress_i is
when CTRL_ADDRESS => rdata_o <= reg_control;
when STATUS_ADDRESS => rdata_o <= reg_status;
- when DATA_ADDRESS => rdata_o <= (rx_buffer'range => rx_buffer, others => '0');
+ when DATA_ADDRESS => rdata_o <= (15 downto 0 => rx_buffer, others => '0');
when INTMASK_ADDRESS => rdata_o <= reg_intmask;
- when others => null;
+ when others => rdata_o <= (others => '0');
end case;
end process output_register;
@@ -253,7 +269,7 @@ begin -- architecture a1
err_lost_rx_data &
busy &
"0" &
- tx_buffer_full &
+ (not tx_buffer_full) &
rx_buffer_full;
tx_data <= tx_buffer;
diff --git a/hdl_spi/tests/Makefile b/hdl_spi/tests/Makefile
index b1f3a9a..84b3292 100644
--- a/hdl_spi/tests/Makefile
+++ b/hdl_spi/tests/Makefile
@@ -6,7 +6,7 @@ TOPLEVEL_LANG ?= vhdl
SRC = $(PWD)/../src
-VHDL_SOURCES=$(SRC)/spi_pkg.vhd $(SRC)/rs_latch.vhd $(SRC)/register.vhd $(SRC)/shift_register.vhd $(SRC)/spi_clkgen.vhd $(SRC)/spi_clkmon.vhd $(SRC)/spi_multiplexor.vhd $(SRC)/spi_slave_ctrl.vhd $(SRC)/spi_master_ctrl.vhd $(SRC)/spi_master.vhd $(SRC)/spi_masterslave.vhd $(SRC)/spi_peripheral.vhd
+VHDL_SOURCES=$(SRC)/spi_pkg.vhd $(SRC)/rs_latch.vhd $(SRC)/register.vhd $(SRC)/shift_register.vhd $(SRC)/spi_clkgen.vhd $(SRC)/spi_clkmon.vhd $(SRC)/spi_slave_ctrl.vhd $(SRC)/spi_master_ctrl.vhd $(SRC)/spi_master.vhd $(SRC)/spi_masterslave.vhd $(SRC)/spi_peripheral.vhd
VCOM_ARGS = -2008
GHDL_ARGS= --std=08
diff --git a/hdl_spi/tests/test_spi_masterslave.py b/hdl_spi/tests/test_spi_masterslave.py
index c85f89f..967a86d 100644
--- a/hdl_spi/tests/test_spi_masterslave.py
+++ b/hdl_spi/tests/test_spi_masterslave.py
@@ -18,7 +18,7 @@ if cocotb.simulator.is_running():
async def init(dut, master: int = 1, tx_en: int = 1):
dut._log.info("Init started!")
- dut.miso_io.value = 0;
+ dut.miso_i.value = 0;
dut.rst_in.value = 0;
dut.lsbfirst_i.value = 0;
dut.clock_polarity_i.value = 0;
@@ -157,7 +157,7 @@ class DutDriver:
@cocotb.test()
async def single_transmit(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(8, RisingEdge, FallingEdge, 10, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -197,7 +197,7 @@ async def single_transmit(dut):
@cocotb.test()
async def lsbfirst(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(8, RisingEdge, FallingEdge, 10, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -250,7 +250,7 @@ async def lsbfirst(dut):
@cocotb.test()
async def rx_tx_disabled(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(8, RisingEdge, FallingEdge, 10, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -305,7 +305,7 @@ async def rx_tx_disabled(dut):
await FallingEdge(dut.clk_i)
await FallingEdge(dut.clk_i)
- assert str(dut.mosi_io.value[0]) == "Z"
+ assert int(dut.mosi_t.value) == 0
await slave.send_data(tx, 8)
await slave.expect_transaction_in(15, "ns")
@@ -314,7 +314,7 @@ async def rx_tx_disabled(dut):
await driver.send_data(rx)
timeout = Timer(10 * (8 + 5), "ns")
- mosi_event = Edge(dut.mosi_io)
+ mosi_event = Edge(dut.mosi_t)
res = await First(timeout, mosi_event)
if res == mosi_event:
@@ -361,7 +361,7 @@ async def perform_multiple_transmits(count, dut, slave, driver, size = 8):
@cocotb.test()
async def multiple_transmits(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(8, RisingEdge, FallingEdge, 10, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -383,7 +383,7 @@ async def multiple_transmits(dut):
@cocotb.test()
async def lost_rx_data(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(8, RisingEdge, FallingEdge, 10, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -407,7 +407,7 @@ async def lost_rx_data(dut):
@cocotb.test()
async def different_clock(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(8, RisingEdge, FallingEdge, 20, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -430,7 +430,7 @@ async def different_clock(dut):
@cocotb.test()
async def inverted_clock(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(8, RisingEdge, FallingEdge, 20, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -454,7 +454,7 @@ async def inverted_clock(dut):
@cocotb.test()
async def shifted_inverted_clock(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(8, FallingEdge, RisingEdge, 20, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -485,7 +485,7 @@ async def shifted_inverted_clock(dut):
@cocotb.test()
async def sixteen_bits(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(16, FallingEdge, RisingEdge, 20, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -512,7 +512,7 @@ async def sixteen_bits(dut):
@cocotb.test()
async def rx_blocking_tx(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(16, RisingEdge, FallingEdge, 10, "ns", csn_pulse = True)
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -537,7 +537,7 @@ async def rx_blocking_tx(dut):
@cocotb.test()
async def csn_pulse(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(16, RisingEdge, FallingEdge, 20, "ns", csn_pulse = True)
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -574,7 +574,6 @@ def spi_tests_runner():
proj_path / "src" / "shift_register.vhd",
proj_path / "src" / "spi_clkgen.vhd",
proj_path / "src" / "spi_clkmon.vhd",
- proj_path / "src" / "spi_multiplexor.vhd",
proj_path / "src" / "spi_slave_ctrl.vhd",
proj_path / "src" / "spi_master_ctrl.vhd",
proj_path / "src" / "spi_master.vhd",
diff --git a/hdl_spi/tests/test_spi_peripheral.py b/hdl_spi/tests/test_spi_peripheral.py
index c577f5d..4e55430 100644
--- a/hdl_spi/tests/test_spi_peripheral.py
+++ b/hdl_spi/tests/test_spi_peripheral.py
@@ -120,7 +120,7 @@ class DutDriver:
@cocotb.test()
async def single_transission(dut):
clk = Clock(dut.clk_i, 5, "ns")
- interface = SpiInterface(dut.csn_io, dut.sck_io, dut.miso_io, dut.mosi_io)
+ interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o)
config = SpiConfig(16, RisingEdge, FallingEdge, 40, "ns")
slave = SpiSlave(interface, config)
driver = DutDriver(dut)
@@ -149,7 +149,7 @@ async def single_transission(dut):
tx = random.randint(0, 255)
await slave.send_data(tx, 16)
- await slave.expect_transaction_in(20, "ns")
+ await slave.expect_transaction_in(100, "ns")
await driver.write(ADDR_DATA, rx)
@@ -181,7 +181,6 @@ def spi_peripheral_tests_runner():
proj_path / "src" / "shift_register.vhd",
proj_path / "src" / "spi_clkgen.vhd",
proj_path / "src" / "spi_clkmon.vhd",
- proj_path / "src" / "spi_multiplexor.vhd",
proj_path / "src" / "spi_slave_ctrl.vhd",
proj_path / "src" / "spi_master_ctrl.vhd",
proj_path / "src" / "spi_master.vhd",
--
2.48.1