From abfea28a8a2555ec22557089a359b3f2b6fd5f23 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Thu, 2 Jan 2025 20:35:59 +0100 Subject: [PATCH] fix: clock polarity on csn falling and rising. Proper wait after csn falling and before csn rising --- hdl_spi/src/spi_clkgen.vhd | 6 +++--- hdl_spi/src/spi_master_ctrl.vhd | 1 + hdl_spi/tests/test_spi_masterslave.py | 7 ++++--- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/hdl_spi/src/spi_clkgen.vhd b/hdl_spi/src/spi_clkgen.vhd index 59f729d..26ba74f 100644 --- a/hdl_spi/src/spi_clkgen.vhd +++ b/hdl_spi/src/spi_clkgen.vhd @@ -116,9 +116,9 @@ begin -- architecture a1 changing <= '1' when curr_counter = 0 and running = '1' and curr_state = SCK_GEN else '0'; next_counter <= selected_divisor - 2 when changing = '1' else - 0 when curr_counter = 0 else - curr_counter - 1 when running = '1' else - selected_divisor - 1; + curr_counter - 1 when running = '1' and curr_counter /= 0 else + selected_divisor - 2 when selected_divisor > 1 else + 0; -- sample_data_o <= '1' when curr_sck = clock_phase_i and changing = '1' else '0'; -- change_data_o <= '1' when curr_sck /= clock_phase_i and changing = '1' else diff --git a/hdl_spi/src/spi_master_ctrl.vhd b/hdl_spi/src/spi_master_ctrl.vhd index 814fc3b..77f184e 100644 --- a/hdl_spi/src/spi_master_ctrl.vhd +++ b/hdl_spi/src/spi_master_ctrl.vhd @@ -175,6 +175,7 @@ begin -- architecture a1 switch_to(NEXT_DATA, 2); else switch_to(NEXT_DATA, 0); + sck_mask_o <= tx_valid_i; end if; end if; when NEXT_DATA => diff --git a/hdl_spi/tests/test_spi_masterslave.py b/hdl_spi/tests/test_spi_masterslave.py index e4d67f0..bdb326f 100644 --- a/hdl_spi/tests/test_spi_masterslave.py +++ b/hdl_spi/tests/test_spi_masterslave.py @@ -456,7 +456,7 @@ async def different_clock_256(dut): async def inverted_clock(dut): clk = Clock(dut.clk_i, 5, "ns") interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o) - config = SpiConfig(8, RisingEdge, FallingEdge, 10, "ns") + config = SpiConfig(8, RisingEdge, FallingEdge, 10, "ns", clock_polarity = 1) slave = SpiSlave(interface, config) driver = DutDriver(dut) @@ -480,7 +480,7 @@ async def inverted_clock(dut): async def shifted_inverted_clock(dut): clk = Clock(dut.clk_i, 5, "ns") interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o) - config = SpiConfig(8, FallingEdge, RisingEdge, 10, "ns") + config = SpiConfig(8, FallingEdge, RisingEdge, 10, "ns", clock_polarity = 1) slave = SpiSlave(interface, config) driver = DutDriver(dut) @@ -502,6 +502,7 @@ async def shifted_inverted_clock(dut): await Timer(100, "ns") dut.clock_phase_i.value = 1 dut.clock_polarity_i.value = 0 + slave.config.clock_polarity = 0 await FallingEdge(dut.clk_i) await perform_multiple_transmits(count, dut, slave, driver) @@ -512,7 +513,7 @@ async def shifted_inverted_clock(dut): async def sixteen_bits(dut): clk = Clock(dut.clk_i, 5, "ns") interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o) - config = SpiConfig(16, FallingEdge, RisingEdge, 10, "ns") + config = SpiConfig(16, FallingEdge, RisingEdge, 10, "ns", clock_polarity = 1) slave = SpiSlave(interface, config) driver = DutDriver(dut) -- 2.48.1