From 9ec022e5f06bb1d572c435809c0614e8e33fadde Mon Sep 17 00:00:00 2001 From: Rutherther Date: Thu, 2 Jan 2025 19:31:23 +0100 Subject: [PATCH] fix: csn was rising too soon for divisors > 2 --- hdl_spi/src/spi_clkgen.vhd | 4 ++-- hdl_spi/src/spi_master_ctrl.vhd | 12 +++++++++--- hdl_spi/src/spi_masterslave.vhd | 24 ++++++++++++------------ 3 files changed, 23 insertions(+), 17 deletions(-) diff --git a/hdl_spi/src/spi_clkgen.vhd b/hdl_spi/src/spi_clkgen.vhd index a96edb6..59f729d 100644 --- a/hdl_spi/src/spi_clkgen.vhd +++ b/hdl_spi/src/spi_clkgen.vhd @@ -92,9 +92,9 @@ begin -- architecture a1 if changing = '1' then if curr_sck = clock_phase_i then - sample_data_o <= '1'; + sample_data_o <= sck_mask_i; else - change_data_o <= '1'; + change_data_o <= sck_mask_i; end if; end if; diff --git a/hdl_spi/src/spi_master_ctrl.vhd b/hdl_spi/src/spi_master_ctrl.vhd index 4801904..814fc3b 100644 --- a/hdl_spi/src/spi_master_ctrl.vhd +++ b/hdl_spi/src/spi_master_ctrl.vhd @@ -171,7 +171,11 @@ begin -- architecture a1 if zero = '1' then transmission_done <= '1'; - switch_to(NEXT_DATA, 0); + if counter_overflow_i = '0' then + switch_to(NEXT_DATA, 2); + else + switch_to(NEXT_DATA, 0); + end if; end if; when NEXT_DATA => csn_o <= '0'; @@ -183,7 +187,7 @@ begin -- architecture a1 sck_mask_o <= '1'; switch_to_shifting(true); ack_tx_got_data <= '1'; - else + elsif zero = '1' then switch_to(IDLE, 0); end if; when others => @@ -269,7 +273,9 @@ begin -- architecture a1 if rx_ready_i = '1' or tx_got_data = '1' then next_rx_state <= RX_INVALID_DATA; rx_block <= '0'; - rx_valid_o <= '0'; + if tx_got_data = '1' then + rx_valid_o <= '0'; + end if; if rx_ready_i = '0' then set_lost_rx_data <= '1'; diff --git a/hdl_spi/src/spi_masterslave.vhd b/hdl_spi/src/spi_masterslave.vhd index 7a51012..451fca5 100644 --- a/hdl_spi/src/spi_masterslave.vhd +++ b/hdl_spi/src/spi_masterslave.vhd @@ -254,18 +254,18 @@ begin -- architecture a1 q_o => tx_serial_data, latch_i => latch_change_data_out); - mosi_t <= slave_mosi_en when slave_en = '1' else - master_mosi_en when master_en = '1' else - '0'; - miso_t <= slave_miso_en when slave_en = '1' else - master_miso_en when master_en = '1' else - '0'; - sck_t <= slave_sck_en when slave_en = '1' else - master_sck_en when master_en = '1' else - '0'; - csn_t <= slave_csn_en when slave_en = '1' else - master_csn_en when master_en = '1' else - '0'; + mosi_t <= not slave_mosi_en when slave_en = '1' else + not master_mosi_en when master_en = '1' else + '0'; + miso_t <= not slave_miso_en when slave_en = '1' else + not master_miso_en when master_en = '1' else + '0'; + sck_t <= not slave_sck_en when slave_en = '1' else + not master_sck_en when master_en = '1' else + '0'; + csn_t <= not slave_csn_en when slave_en = '1' else + not master_csn_en when master_en = '1' else + '0'; mosi_o <= tx_serial_data(0) when master_en = '1' else '0' when slave_en = '1' else -- 2.48.1