From 98fdc2a71b1659c3d65e838503aa607502a8bb09 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Thu, 2 Jan 2025 20:35:36 +0100 Subject: [PATCH] tests: add proper checks for clock polarity before and after csn --- hdl_spi/models/spi_models.py | 14 ++++++++++---- hdl_spi/tests/test_spi_peripheral.py | 4 ++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/hdl_spi/models/spi_models.py b/hdl_spi/models/spi_models.py index a69bdaa..6d0fac5 100644 --- a/hdl_spi/models/spi_models.py +++ b/hdl_spi/models/spi_models.py @@ -61,6 +61,7 @@ class SpiConfig: sck_period: int sck_period_unit: str csn_pulse: bool = False + clock_polarity: int = 0 class SpiSlave: def __init__(self, spi: SpiInterface, config: SpiConfig): @@ -140,6 +141,8 @@ class SpiSlave: continue # csn fell + if int(self.sck.value) != self.config.clock_polarity: + raise Exception("The clock is not at correct polarity after CSN falling!") first = True while not self.transactions.empty(): @@ -192,10 +195,11 @@ class SpiSlave: if self.config.csn_pulse: break - sampling = self.config.sampling(self.sck) - csn_rising = RisingEdge(self.csn) - timeout = Timer(self.config.sck_period * 2, self.config.sck_period_unit) - res = await First(shifting, csn_rising, timeout) + if int(self.sck.value) != self.config.clock_polarity: + sampling = self.config.sampling(self.sck) + csn_rising = RisingEdge(self.csn) + timeout = Timer(self.config.sck_period * 2, self.config.sck_period_unit) + res = await First(shifting, csn_rising, timeout) if res == csn_rising: raise Exception("CSN rising too soon!") @@ -219,6 +223,8 @@ class SpiSlave: raise Exception("Got sck edge when csn rising was expected") self._log.info("csn is rising") + if int(self.sck.value) != self.config.clock_polarity: + raise Exception("The clock is not at correct polarity after CSN rising!") self.tx.value = cocotb.handle.Release() diff --git a/hdl_spi/tests/test_spi_peripheral.py b/hdl_spi/tests/test_spi_peripheral.py index 8bab1d1..d9485de 100644 --- a/hdl_spi/tests/test_spi_peripheral.py +++ b/hdl_spi/tests/test_spi_peripheral.py @@ -129,7 +129,7 @@ class DutDriver: async def single_transmission(dut): clk = Clock(dut.clk_i, 5, "ns") interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o) - config = SpiConfig(16, RisingEdge, FallingEdge, 40, "ns") + config = SpiConfig(16, RisingEdge, FallingEdge, 40, "ns", clock_polarity = 1) slave = SpiSlave(interface, config) driver = DutDriver(dut) @@ -177,7 +177,7 @@ async def single_transmission(dut): async def interrupt(dut): clk = Clock(dut.clk_i, 5, "ns") interface = SpiInterface(dut.csn_o, dut.sck_o, dut.miso_i, dut.mosi_o) - config = SpiConfig(16, RisingEdge, FallingEdge, 10, "ns") + config = SpiConfig(16, RisingEdge, FallingEdge, 10, "ns", clock_polarity = 1) slave = SpiSlave(interface, config) driver = DutDriver(dut) -- 2.48.1