From 55fdca2b9c6e0468cb4a26040791ad6faf48b481 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Fri, 27 Dec 2024 22:56:31 +0100 Subject: [PATCH] fix: sck generation Sampling and changing was offset by one clock, which is unnecesary. The clock wasn't correct frequency, ie. divisor 2 led to division by 3 --- hdl_spi/src/spi_clkgen.vhd | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/hdl_spi/src/spi_clkgen.vhd b/hdl_spi/src/spi_clkgen.vhd index d66a380..8503077 100644 --- a/hdl_spi/src/spi_clkgen.vhd +++ b/hdl_spi/src/spi_clkgen.vhd @@ -40,11 +40,6 @@ architecture a1 of spi_clkgen is signal curr_sck : std_logic; signal next_sck : std_logic; - signal next_sample_data : std_logic; - signal curr_sample_data : std_logic; - - signal next_change_data : std_logic; - signal curr_change_data : std_logic; begin -- architecture a1 set_data: process (clk_i) is @@ -54,14 +49,10 @@ begin -- architecture a1 curr_running <= '0'; curr_sck <= '0'; curr_counter <= 0; - curr_sample_data <= '0'; - curr_change_data <= '0'; else curr_running <= next_running; curr_sck <= next_sck; curr_counter <= next_counter; - curr_sample_data <= next_sample_data; - curr_change_data <= next_change_data; end if; end if; end process set_data; @@ -70,13 +61,13 @@ begin -- architecture a1 changing <= '1' when curr_counter = 0 and curr_running = '1' else '0'; - next_counter <= selected_divisor - 1 when changing = '1' else + next_counter <= selected_divisor - 2 when changing = '1' else 0 when curr_counter = 0 else curr_counter - 1 when curr_running = '1' else selected_divisor - 1; - next_sample_data <= '1' when curr_sck = clock_phase_i and changing = '1' else '0'; - next_change_data <= '1' when curr_sck /= clock_phase_i and changing = '1' else '0'; + sample_data_o <= sck_mask_i when curr_sck = clock_phase_i and changing = '1' else '0'; + change_data_o <= sck_mask_i when curr_sck /= clock_phase_i and changing = '1' else '0'; next_sck <= not curr_sck when changing = '1' else curr_sck when curr_running = '1' else @@ -88,8 +79,6 @@ begin -- architecture a1 curr_sck when clock_polarity_i = '0' else not curr_sck; - clock_rising_o <= curr_sample_data; - sample_data_o <= curr_sample_data and sck_mask_i; - change_data_o <= curr_change_data and sck_mask_i; + clock_rising_o <= '1' when curr_sck = clock_phase_i and changing = '1' else '0'; end architecture a1; -- 2.48.1