From 21e3de55dc52c5a3a0d5b5afc70ab42cdff0ff65 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Sun, 29 Dec 2024 13:38:44 +0100 Subject: [PATCH] fix: master didn't go to invalid data when data are read on first cycle of ready --- hdl_spi/src/spi_master_ctrl.vhd | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hdl_spi/src/spi_master_ctrl.vhd b/hdl_spi/src/spi_master_ctrl.vhd index ed84ddb..cdc9337 100644 --- a/hdl_spi/src/spi_master_ctrl.vhd +++ b/hdl_spi/src/spi_master_ctrl.vhd @@ -276,7 +276,9 @@ begin -- architecture a1 if rx_ready_i = '0' then rx_block <= rx_block_on_full_i; end if; - next_rx_state <= RX_GOT_DATA; + if rx_ready_i = '0' then + next_rx_state <= RX_GOT_DATA; + end if; rx_valid_o <= '1'; -- TODO check end if; when others => -- 2.48.1