From 1e50c8368c7f12f9f6be6f96715683d607a1f162 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Sat, 28 Dec 2024 19:42:57 +0100 Subject: [PATCH] fix: clkgen for various phases and polarities --- hdl_spi/src/spi_clkgen.vhd | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hdl_spi/src/spi_clkgen.vhd b/hdl_spi/src/spi_clkgen.vhd index 8503077..5f93090 100644 --- a/hdl_spi/src/spi_clkgen.vhd +++ b/hdl_spi/src/spi_clkgen.vhd @@ -14,6 +14,7 @@ entity spi_clkgen is clk_i : in std_logic; rst_in : in std_logic; start_i : in std_logic; + -- next_data_i : in std_logic; div_sel_i : in std_logic_vector(DIVISORS_LOG2 - 1 downto 0); clock_polarity_i : in std_logic; clock_phase_i : in std_logic; @@ -67,11 +68,14 @@ begin -- architecture a1 selected_divisor - 1; sample_data_o <= sck_mask_i when curr_sck = clock_phase_i and changing = '1' else '0'; - change_data_o <= sck_mask_i when curr_sck /= clock_phase_i and changing = '1' else '0'; + change_data_o <= sck_mask_i when curr_sck /= clock_phase_i and changing = '1' else + '1' when clock_phase_i = '0' and start_i = '1' and curr_running = '0' else + -- '1' when next_data_i = '1' else + '0'; next_sck <= not curr_sck when changing = '1' else curr_sck when curr_running = '1' else - clock_polarity_i; + '0'; next_running <= start_i; -- 2.48.1