user.org user spi_axi_perpih 1.0 S00_AXI_RST RST s00_axi_aresetn POLARITY ACTIVE_LOW S00_AXI_CLK CLK s00_axi_aclk ASSOCIATED_BUSIF S00_AXI ASSOCIATED_RESET s00_axi_aresetn s00_axi_aclk CLK s00_axi_aclk ASSOCIATED_RESET s00_axi_aresetn ASSOCIATED_BUSIF s00_axi s00_axi_aresetn RST s00_axi_aresetn POLARITY ACTIVE_LOW S00_AXI AWADDR s00_axi_awaddr AWPROT s00_axi_awprot AWVALID s00_axi_awvalid AWREADY s00_axi_awready WDATA s00_axi_wdata WSTRB s00_axi_wstrb WVALID s00_axi_wvalid WREADY s00_axi_wready BRESP s00_axi_bresp BVALID s00_axi_bvalid BREADY s00_axi_bready ARADDR s00_axi_araddr ARPROT s00_axi_arprot ARVALID s00_axi_arvalid ARREADY s00_axi_arready RDATA s00_axi_rdata RRESP s00_axi_rresp RVALID s00_axi_rvalid RREADY s00_axi_rready spi_interrupt INTERRUPT interrupt S00_AXI S00_AXI_reg 0 4096 32 register OFFSET_BASE_PARAM C_S00_AXI_BASEADDR OFFSET_HIGH_PARAM C_S00_AXI_HIGHADDR control 0 4 en master tx_en rx_en clock_polarity clock_phase pulse_csn lsbfirst size_sel div_sel intmask 4 4 data 12 4 status 8 4 xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog spi_axi_perpih xilinx_verilogsynthesis_view_fileset viewChecksum 5a081c5b xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog spi_axi_perpih xilinx_verilogbehavioralsimulation_view_fileset viewChecksum 5a081c5b xilinx_softwaredriver Software Driver :vivado.xilinx.com:sw.driver xilinx_softwaredriver_view_fileset viewChecksum cff73a53 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 080b65eb bd_tcl Block Diagram :vivado.xilinx.com:block.diagram bd_tcl_view_fileset viewChecksum 45a2f450 mosi_o out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation miso_o out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation csn_o out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation sck_o out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mosi_i in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation miso_i in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation csn_i in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation sck_i in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mosi_t out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation miso_t out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation csn_t out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation sck_t out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation interrupt out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_aclk in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_aresetn in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_awaddr in 4 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 s00_axi_awprot in 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 s00_axi_awvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 s00_axi_awready out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_wdata in 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 s00_axi_wstrb in 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 1 s00_axi_wvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 s00_axi_wready out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_bresp out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_bvalid out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_bready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 s00_axi_araddr in 4 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 s00_axi_arprot in 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 s00_axi_arvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 s00_axi_arready out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_rdata out 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_rresp out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_rvalid out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_rready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus 32 C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus 5 choice_list_6fc15197 32 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_verilogsynthesis_view_fileset hdl/spi_axi_perpih_slave_lite_v1_0_S00_AXI.v verilogSource ../../hdl_spi/src/rs_latch.vhd vhdlSource-2008 ../../hdl_spi/src/spi_pkg.vhd vhdlSource ../../hdl_spi/src/spi_master_ctrl.vhd vhdlSource-2008 ../../hdl_spi/src/spi_clkgen.vhd vhdlSource-2008 ../../hdl_spi/src/shift_register.vhd vhdlSource-2008 ../../hdl_spi/src/register.vhd vhdlSource-2008 ../../hdl_spi/src/spi_clkmon.vhd vhdlSource-2008 ../../hdl_spi/src/spi_slave_ctrl.vhd vhdlSource-2008 ../../hdl_spi/src/spi_masterslave.vhd vhdlSource-2008 ../../hdl_spi/src/spi_peripheral.vhd vhdlSource-2008 CHECKSUM_61839fda hdl/spi_axi_perpih.v verilogSource CHECKSUM_d1de95ee xilinx_verilogbehavioralsimulation_view_fileset hdl/spi_axi_perpih_slave_lite_v1_0_S00_AXI.v verilogSource ../../hdl_spi/src/rs_latch.vhd vhdlSource-2008 ../../hdl_spi/src/spi_pkg.vhd vhdlSource ../../hdl_spi/src/spi_master_ctrl.vhd vhdlSource-2008 ../../hdl_spi/src/spi_clkgen.vhd vhdlSource-2008 ../../hdl_spi/src/shift_register.vhd vhdlSource-2008 ../../hdl_spi/src/register.vhd vhdlSource-2008 ../../hdl_spi/src/spi_clkmon.vhd vhdlSource-2008 ../../hdl_spi/src/spi_slave_ctrl.vhd vhdlSource-2008 ../../hdl_spi/src/spi_masterslave.vhd vhdlSource-2008 ../../hdl_spi/src/spi_peripheral.vhd vhdlSource-2008 hdl/spi_axi_perpih.v verilogSource xilinx_softwaredriver_view_fileset drivers/spi_axi_perpih_v1_0/data/spi_axi_perpih.mdd mdd driver_mdd drivers/spi_axi_perpih_v1_0/data/spi_axi_perpih.tcl tclSource driver_tcl drivers/spi_axi_perpih_v1_0/src/Makefile driver_src drivers/spi_axi_perpih_v1_0/src/spi_axi_perpih.h cSource driver_src drivers/spi_axi_perpih_v1_0/src/spi_axi_perpih.c cSource driver_src drivers/spi_axi_perpih_v1_0/src/spi_axi_perpih_selftest.c cSource driver_src xilinx_xpgui_view_fileset xgui/spi_axi_perpih_v1_0.tcl tclSource CHECKSUM_080b65eb XGUI_VERSION_2 bd_tcl_view_fileset bd/bd.tcl tclSource SPI axi peripheral memory mapped C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus 32 false C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus 5 false C_S00_AXI_BASEADDR C S00 AXI BASEADDR 0xFFFFFFFF false C_S00_AXI_HIGHADDR C S00 AXI HIGHADDR 0x00000000 false Component_Name spi_axi_perpih_v1_0 zynq AXI_Peripheral spi_axi_perpih_v1.0 12 2025-01-02T15:09:39Z 2024.1