library ieee;
use ieee.std_logic_1164.all;
use work.spi_pkg.all;

entity spi_slave_ctrl is

  generic (
    SIZES            : natural_vector := (8, 16);
    SIZES_2LOG       : natural := 1;
    CSN_PULSE_CYCLES : natural := 1
  );

  port (
    clk_i                : in  std_logic;
    rst_in               : in  std_logic;
    en_i                 : in  std_logic;
    size_sel_i           : in  std_logic_vector(SIZES_2LOG - 1 downto 0);
    pulse_csn_i          : in  std_logic;
    clock_rising_i       : in  std_logic;
    rx_block_on_full_i   : in  std_logic;
    rx_en_i              : in  std_logic;
    rx_valid_o           : out std_logic;
    rx_ready_i           : in  std_logic;
    tx_en_i              : in  std_logic;
    tx_valid_i           : in  std_logic;
    tx_ready_o           : out std_logic;
    busy_o               : out std_logic;
    err_lost_rx_data_o   : out std_logic;
    clear_lost_rx_data_i : in  std_logic;
    rst_on               : out std_logic;
    csn_o                : out std_logic;
    csn_en_o             : out std_logic;
    mosi_en_o            : out std_logic;
    miso_en_o            : out std_logic;
    sck_mask_o           : out std_logic;
    sck_en_o             : out std_logic;
    gen_clk_en_o         : out std_logic;
    latch_tx_data_o      : out std_logic);

end entity spi_slave_ctrl;

architecture a1 of spi_slave_ctrl is

begin  -- architecture a1

  csn_o <= '0';

  sck_mask_o <= '0';

  gen_clk_en_o <= '0';
  latch_tx_data_o <= '0';
  rst_on <= '0';
  err_lost_rx_data_o <= '0';
  busy_o <= '0';
  rx_valid_o <= '0';
  tx_ready_o <= '0';

  miso_en_o <= '0';
  mosi_en_o <= '0';
  sck_en_o <= '0';
  csn_en_o <= '0';

end architecture a1;