library ieee;
use ieee.std_logic_1164.all;


entity reg is

  generic (
    SIZE : natural := 1);

  port (
    clk_i   : in  std_logic;
    rst_in  : in  std_logic;
    d_i     : in  std_logic_vector(SIZE - 1 downto 0);
    q_o     : out std_logic_vector(SIZE - 1 downto 0);
    latch_i : in  std_logic);

end entity reg;

architecture a1 of reg is

begin  -- architecture a1

  set_q: process (clk_i) is
  begin  -- process set_q
    if rising_edge(clk_i) then          -- rising clock edge
      if rst_in = '0' then              -- synchronous reset (active low)
        q_o <= (others => '0');
      elsif latch_i = '1' then
        q_o <= d_i;
      end if;
    end if;
  end process set_q;

end architecture a1;