library ieee; use ieee.std_logic_1164.all; entity spi_multiplexor is port ( en_i : in std_logic; mosi_en_i : in std_logic; miso_en_i : in std_logic; sck_en_i : in std_logic; csn_en_i : in std_logic; mosi_i : in std_logic; miso_i : in std_logic; sck_i : in std_logic; csn_i : in std_logic; mosi_o : out std_logic; miso_o : out std_logic; sck_o : out std_logic; csn_o : out std_logic; rx_valid_i : in std_logic; rx_valid_o : out std_logic; tx_ready_i : in std_logic; tx_ready_o : out std_logic; busy_i : in std_logic; busy_o : out std_logic; err_lost_rx_data_i : in std_logic; err_lost_rx_data_o : out std_logic; rst_in : in std_logic; rst_on : out std_logic; latch_tx_data_i : in std_logic; latch_tx_data_o : out std_logic; latch_sample_data_i : in std_logic; latch_sample_data_o : out std_logic; latch_change_data_i : in std_logic; latch_change_data_o : out std_logic; rx_serial_i : in std_logic; rx_serial_o : out std_logic); end entity spi_multiplexor; architecture a1 of spi_multiplexor is begin -- architecture a1 mosi_o <= mosi_i when mosi_en_i = '1' and en_i = '1' else 'Z'; miso_o <= miso_i when miso_en_i = '1' and en_i = '1' else 'Z'; sck_o <= sck_i when sck_en_i = '1' and en_i = '1' else'Z'; csn_o <= csn_i when csn_en_i = '1' and en_i = '1' else'Z'; rx_valid_o <= rx_valid_i when en_i = '1' else'Z'; tx_ready_o <= tx_ready_i when en_i = '1' else'Z'; busy_o <= busy_i when en_i = '1' else'Z'; err_lost_rx_data_o <= err_lost_rx_data_i when en_i = '1' else'Z'; rst_on <= rst_in when en_i = '1' else'Z'; latch_tx_data_o <= latch_tx_data_i when en_i = '1' else'Z'; latch_sample_data_o <= latch_sample_data_i when en_i = '1' else'Z'; latch_change_data_o <= latch_change_data_i when en_i = '1' else'Z'; rx_serial_o <= rx_serial_i when en_i = '1' else 'Z'; end architecture a1;