# Copyright (C) 2022 Xilinx, Inc # SPDX-License-Identifier: BSD-3-Clause #create_generated_clock -name clk50khz -source [get_pins toplevel_i/top_0/clk_i] -divide_by 1000 [get_pins toplevel_i/top_0/U0/clk_divider/CLK] #create_generated_clock -name sftclk -source [get_pins toplevel_i/top_0/U0/clk_divider/CLK] -edges {2 3 4} [get_ports sftclk] ## Switches #set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {sw[0]}] #set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports {sw[1]}] ## Audio #set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports IIC_1_scl_io] #set_property PULLUP true [get_ports IIC_1_scl_io]; #set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports IIC_1_sda_io] #set_property PULLUP true [get_ports IIC_1_sda_io]; #set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports audio_clk_10MHz]; #set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports bclk]; #set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports lrclk]; #set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports sdata_o]; #set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports sdata_i]; #set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports {codec_addr[0]}] #set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {codec_addr[1]}] ## Buttons # set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports onoff] # set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports rst] #set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports onoff] #set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS33} [get_ports rst] #set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports {btns_4bits_tri_i[2]}] #set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS33} [get_ports {btns_4bits_tri_i[3]}] ### LEDs #set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {led0}] #set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {led1}] #set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {led2}] #set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {leds_4bits_tri_o[3]}] ## RGBLEDs #set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { rgbleds_6bits_tri_o[0] }]; #set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { rgbleds_6bits_tri_o[1] }]; #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { rgbleds_6bits_tri_o[2] }]; #set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { rgbleds_6bits_tri_o[3] }]; #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { rgbleds_6bits_tri_o[4] }]; #set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { rgbleds_6bits_tri_o[5] }]; ## Pmoda ## RPi GPIO 7-0 are shared with pmoda_rpi_gpio_tri_io[7:0] set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports csn] set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sck] set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports mosi] set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports miso] #set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {pmoda_rpi_gpio_tri_io[5]}] #set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {pmoda_rpi_gpio_tri_io[4]}] #set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports {pmoda_rpi_gpio_tri_io[7]}] #set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {pmoda_rpi_gpio_tri_io[6]}] #set_property PULLUP true [get_ports {pmoda_rpi_gpio_tri_io[2]}] #set_property PULLUP true [get_ports {pmoda_rpi_gpio_tri_io[3]}] #set_property PULLUP true [get_ports {pmoda_rpi_gpio_tri_io[6]}] #set_property PULLUP true [get_ports {pmoda_rpi_gpio_tri_io[7]}] ## Pmodb #set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports {pmodb_gpio_tri_io[1]}] #set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports {pmodb_gpio_tri_io[0]}] #set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {pmodb_gpio_tri_io[3]}] #set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {pmodb_gpio_tri_io[2]}] #set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports {pmodb_gpio_tri_io[5]}] #set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {pmodb_gpio_tri_io[4]}] #set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {pmodb_gpio_tri_io[7]}] #set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {pmodb_gpio_tri_io[6]}] #set_property PULLUP true [get_ports {pmodb_gpio_tri_io[2]}] #set_property PULLUP true [get_ports {pmodb_gpio_tri_io[3]}] #set_property PULLUP true [get_ports {pmodb_gpio_tri_io[6]}] #set_property PULLUP true [get_ports {pmodb_gpio_tri_io[7]}] ## Arduino GPIO set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {arduino_a0_a5_tri_io[0]}] set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {arduino_ar0_a5_tri_io[1]}] set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {arduino_a0_a5_tri_io[2]}] set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports {arduino_a0_a5_tri_io[3]}] set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {arduino_a0_a5_tri_io[4]}] set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {arduino_a0_a5_tri_io[5]}] #set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[6]}] #set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports sftclk] #set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports ds] #set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[9]}] #set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[10]}] #set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[11]}] #set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[12]}] #set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[13]}] #set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[14]}] #set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[15]}] #set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[16]}] #set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[17]}] #set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[18]}] #set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[19]}] ## Arduino direct I2C #set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports arduino_direct_iic_scl_io] #set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports arduino_direct_iic_sda_io] #set_property PULLUP true [get_ports arduino_direct_iic_scl_io] #set_property PULLUP true [get_ports arduino_direct_iic_sda_io] ## Arduino direct SPI #set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports arduino_direct_spi_io1_io] #set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports arduino_direct_spi_io0_io] #set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports arduino_direct_spi_sck_io] #set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports arduino_direct_spi_ss_io] ## Arduino analog channels #set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports Vaux1_v_n] #set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports Vaux1_v_p] #set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports Vaux9_v_n] #set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports Vaux9_v_p] #set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports Vaux6_v_n] #set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports Vaux6_v_p] #set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports Vaux15_v_n] #set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports Vaux15_v_p] #set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS33} [get_ports Vaux5_v_n] #set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS33} [get_ports Vaux5_v_p] #set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports Vaux13_v_n] #set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports Vaux13_v_p] ## HDMI signals #create_clock -period 8.334 -waveform {0.000 4.167} [get_ports hdmi_in_clk_p] ## HDMI RX #set_property -dict {PACKAGE_PIN P19 IOSTANDARD TMDS_33} [get_ports hdmi_in_clk_n] #set_property -dict {PACKAGE_PIN N18 IOSTANDARD TMDS_33} [get_ports hdmi_in_clk_p] #set_property -dict {PACKAGE_PIN W20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_n[0]}] #set_property -dict {PACKAGE_PIN V20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_p[0]}] #set_property -dict {PACKAGE_PIN U20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_n[1]}] #set_property -dict {PACKAGE_PIN T20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_p[1]}] #set_property -dict {PACKAGE_PIN P20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_n[2]}] #set_property -dict {PACKAGE_PIN N20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_p[2]}] #set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {hdmi_in_hpd[0]}] #set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports hdmi_in_ddc_scl_io] #set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports hdmi_in_ddc_sda_io] ### HDMI TX #set_property -dict {PACKAGE_PIN L17 IOSTANDARD TMDS_33} [get_ports hdmi_out_clk_n] #set_property -dict {PACKAGE_PIN L16 IOSTANDARD TMDS_33} [get_ports hdmi_out_clk_p] #set_property -dict {PACKAGE_PIN K18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_n[0]}] #set_property -dict {PACKAGE_PIN K17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_p[0]}] #set_property -dict {PACKAGE_PIN J19 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_n[1]}] #set_property -dict {PACKAGE_PIN K19 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_p[1]}] #set_property -dict {PACKAGE_PIN H18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_n[2]}] #set_property -dict {PACKAGE_PIN J18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_p[2]}] #set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {hdmi_out_hpd[0]}] ## Raspberry PI ## RPI_IDE Pin# | RP Connector | Schematic Name | Dual Functionality ## 1 | 3v3 | NA ## 3 | GPIO2 | JA4_P | I2C1_SDA ## 5 | GPIO3 | JA4_N | I2C1_SCL ## 7 | GPIO4 | JA1_P | GCLK0 ## 9 | GROUND | NA ## 11 | GPIO17 | RP_IO17_R ## 13 | GPIO27 | RP_IO27_R ## 15 | GPIO22 | RP_IO22_R ## 17 | 3v3 | NA ## 19 | GPIO10 | RP_IO10_R | SPIO0_MOSI ## 21 | GPIO9 | RP_IO09_R | SPIO0_MISO ## 23 | GPIO11 | RP_IO11_R | SPIO0_SCLK ## 25 | GROUND | NA ## 27 | GPIO0 | JA2_P | I2C0_SDA ID EEPROM ## 29 | GPIO5 | JA1_N | GCLK1 ## 31 | GPIO6 | JA3_P | GCLK2 ## 33 | GPIO13 | RP_IO13_R | PWM1 ## 35 | GPIO19 | RP_IO19_R | SPIO1_MISO ## 37 | GPIO26 | RP_IO26_R ## 39 | GROUND | NA ## 2 | 5V | NA ## 4 | 5V | NA ## 6 | GROUND | NA ## 8 | GPIO14 | RP_IO14_R | UART0_TXD ## 10 | GPIO15 | RP_IO15_R | UART0_RXD ## 12 | GPIO18 | RP_IO18_R | PCM_CLK ## 14 | GROUND | NA ## 16 | GPIO23 | RP_IO23_R ## 18 | GPIO24 | RP_IO24_R ## 20 | GROUND | NA ## 22 | GPIO25 | RP_IO25_R ## 24 | GPIO8 | RP_IO08_R | SPIO0_CE0_N ## 26 | GPIO7 | JA3_N | SPIO0_CE1_N ## 28 | GPIO1 | JA2_N | I2C0_SDC ID EEPROM ## 30 | GROUND | NA ## 32 | GPIO12 | RP_IO12_R | PWM0 ## 34 | GROUND | NA ## 36 | GPIO16 | RP_IO16_R | SPIO1_CE2_N ## 38 | GPIO20 | RP_IO20_R | SPIO1_MOSI ## 40 | GPIO21 | RP_IO21_R | SPIO1_SCLK ## RPi GPIO 27-8 are mapped to rpi_gpio_tri_io[19:0] #set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[0] }]; #set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[1] }]; #set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[2] }]; #set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[3] }]; #set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[4] }]; #set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[5] }]; #set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[6] }]; #set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[7] }]; #set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[8] }]; #set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[9] }]; #set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[10] }]; #set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[11] }]; #set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[12] }]; #set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[13] }]; #set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[14] }]; #set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[15] }]; #set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[16] }]; #set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[17] }]; #set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[18] }]; #set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { rpi_gpio_tri_io[19] }]; set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr_reg_n_0_[2]}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr_reg_n_0_[1]}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr_reg_n_0_[0]}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr_reg_n_0_[0]}] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_wready_reg_0] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr_reg_n_0_[2]}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr_reg_n_0_[1]}] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/periph_read_reg_n_0] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/fill_tx_buffer_reg_0] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/fill_tx_buffer_reg_1] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/fill_tx_buffer_reg_2] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr[0]_i_1_n_0}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr[1]_i_1_n_0}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr[2]_i_2_n_0}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr[0]_i_1_n_0}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr[1]_i_1_n_0}] connect_debug_port u_ila_0/probe31 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/periph_read_reg_n_0]] connect_debug_port u_ila_0/probe6 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr[0]_i_1_n_0}]] connect_debug_port u_ila_0/probe7 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr[1]_i_1_n_0}]] connect_debug_port u_ila_0/probe9 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr[2]_i_2_n_0}]] connect_debug_port u_ila_0/probe10 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr_reg_n_0_[0]}]] connect_debug_port u_ila_0/probe11 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr_reg_n_0_[1]}]] connect_debug_port u_ila_0/probe12 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr_reg_n_0_[2]}]] connect_debug_port u_ila_0/probe13 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr[0]_i_1_n_0}]] connect_debug_port u_ila_0/probe14 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr[1]_i_1_n_0}]] connect_debug_port u_ila_0/probe16 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr_reg_n_0_[0]}]] connect_debug_port u_ila_0/probe17 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr_reg_n_0_[1]}]] connect_debug_port u_ila_0/probe18 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr_reg_n_0_[2]}]] connect_debug_port u_ila_0/probe21 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_wready_reg_0]] connect_debug_port u_ila_0/probe25 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/fill_tx_buffer_reg_0]] connect_debug_port u_ila_0/probe26 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/fill_tx_buffer_reg_1]] connect_debug_port u_ila_0/probe27 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/fill_tx_buffer_reg_2]] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[1]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/mosi_i] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[6]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[9]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[10]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/state_read[1]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[17]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wvalid] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[25]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[10]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[3]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[28]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[26]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[11]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[26]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[9]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[21]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/miso_i] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_aresetn] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[29]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/csn_t] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awaddr[2]_i_1_n_0}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[7]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[8]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[11]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[24]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[2]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[4]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_awvalid] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[19]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[12]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[1]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[9]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[14]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[25]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[16]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[14]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[11]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[29]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_awaddr[2]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_rvalid_reg_0] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[14]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[15]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[7]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/periph_raddress[1]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[16]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[23]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[31]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[8]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[27]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[31]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[20]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[16]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[24]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[31]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[12]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[18]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[26]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/state_read[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[5]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[17]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[19]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[15]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[1]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[30]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[22]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[17]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[21]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[23]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[19]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[7]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[15]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/mosi_t] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[12]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[13]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[18]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/periph_raddress[2]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/periph_raddress[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[9]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_aclk] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[14]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[21]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[29]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[28]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[18]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[24]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[23]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[11]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[15]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[13]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[5]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[20]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[22]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[25]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[10]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/miso_o] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[2]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_araddr[2]_i_1_n_0}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[6]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst_n_0] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[13]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[20]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[6]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[22]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/sck_i] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rready] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[29]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[14]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[10]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[2]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[12]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_awaddr[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_awaddr[1]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/mosi_o] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/axi_awready_reg_0] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[11]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[8]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[9]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[19]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/p_0_in[1]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[12]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[27]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[7]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/sck_o] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[30]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[5]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[30]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[13]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[25]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[17]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[24]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/interrupt] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/fill_tx_buffer_i_1_n_0] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[3]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[4]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[27]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[28]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/csn_o] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[16]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[5]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/p_0_in[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/p_0_in[2]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[18]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[26]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_rdata[31]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[28]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[8]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[13]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[30]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[27]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[6]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[15]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask[8]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/s00_axi_wdata[23]}] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/clock_polarity] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[20]}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[10]}] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_17] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[22]}] set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[21]}] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_25] connect_debug_port u_ila_0/probe0 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[10]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[20]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[21]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control[22]}]] connect_debug_port u_ila_0/probe8 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/clock_polarity]] connect_debug_port u_ila_0/probe22 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_9]] connect_debug_port u_ila_0/probe29 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_17]] connect_debug_port u_ila_0/probe30 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_25]] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_8] set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_16] connect_debug_port u_ila_0/probe21 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_8]] connect_debug_port u_ila_0/probe28 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_16]] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/s00_axi_aclk] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/miso_o] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/mosi_t] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/fill_tx_buffer_reg_n_0] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/csn_o] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask_reg_n_0_[4]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/master] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_3] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_4] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/mosi_o] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control_reg[1]_0}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control_reg_n_0_[0]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_en] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control_reg_n_0_[10]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[3]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/s00_axi_aresetn_0] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/s00_axi_rdata[3]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/sck_i] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/sck_o] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/clear_lost_rx_data] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control_reg_n_0_[22]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/interrupt] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_10] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_1] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/pulse_csn] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/data1] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer[4]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/periph_raddress[2]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_en] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[2]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[3]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[13]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[4]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[8]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[9]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[11]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[12]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_13] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/miso_i] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/lsbfirst] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_2] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_6] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_14] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_15] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control_reg_n_0_[20]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_27] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_control_reg_n_0_[21]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask_reg_n_0_[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/reg_intmask_reg_n_0_[3]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/s00_axi_rdata[4]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer_full] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/data0] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/clear_rx_buffer_full_reg_n_0] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_12] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/periph_raddress[1]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_11] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/periph_raddress[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[15]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[14]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer_0] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/rx_buffer_full] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/s00_axi_aresetn] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[0]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[1]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[6]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[7]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[5]}] set_property MARK_DEBUG false [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/tx_buffer[10]}] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_9] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/mosi_i] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/clock_polarity_i] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_5] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_7] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/clock_phase] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave_n_26] set_property MARK_DEBUG false [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/p_1_in] set_property MARK_DEBUG true [get_nets csn_i_0] set_property MARK_DEBUG true [get_nets csn_t_0] set_property MARK_DEBUG true [get_nets csn_o_0] set_property MARK_DEBUG true [get_nets miso_i_0] set_property MARK_DEBUG true [get_nets sck_o_0] set_property MARK_DEBUG true [get_nets sck_t_0] set_property MARK_DEBUG true [get_nets sck_i_0] set_property MARK_DEBUG true [get_nets mosi_o_0] set_property MARK_DEBUG true [get_nets mosi_t_0] set_property MARK_DEBUG true [get_nets mosi_i_0] set_property MARK_DEBUG true [get_nets miso_t_0] set_property MARK_DEBUG true [get_nets miso_o_0] create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] set_property C_DATA_DEPTH 32768 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list toplevel_i/processing_system7_0/inst/FCLK_CLK0]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 1 [get_debug_ports u_ila_0/probe0] connect_debug_port u_ila_0/probe0 [get_nets [list csn_o_0]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] set_property port_width 1 [get_debug_ports u_ila_0/probe1] connect_debug_port u_ila_0/probe1 [get_nets [list csn_t_0]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] set_property port_width 1 [get_debug_ports u_ila_0/probe2] connect_debug_port u_ila_0/probe2 [get_nets [list miso_i_0]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 1 [get_debug_ports u_ila_0/probe3] connect_debug_port u_ila_0/probe3 [get_nets [list miso_o_0]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 1 [get_debug_ports u_ila_0/probe4] connect_debug_port u_ila_0/probe4 [get_nets [list mosi_i_0]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 1 [get_debug_ports u_ila_0/probe5] connect_debug_port u_ila_0/probe5 [get_nets [list mosi_o_0]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 1 [get_debug_ports u_ila_0/probe6] connect_debug_port u_ila_0/probe6 [get_nets [list mosi_t_0]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 1 [get_debug_ports u_ila_0/probe7] connect_debug_port u_ila_0/probe7 [get_nets [list sck_i_0]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 1 [get_debug_ports u_ila_0/probe8] connect_debug_port u_ila_0/probe8 [get_nets [list sck_o_0]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 1 [get_debug_ports u_ila_0/probe9] connect_debug_port u_ila_0/probe9 [get_nets [list sck_t_0]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] connect_debug_port dbg_hub/clk [get_nets u_ila_0_FCLK_CLK0]