spi_master
  SIZES (8, 16 default)
  SIZES_LOG2 1

  DIVISORS_LOG2 3
  DIVISORS (2, 4, 8, 16, 32, 64, 128, 256)

  CSN_PULSE_CYCLES (1 - divided clock cycle)

  INOUTS
    sck, miso, mosi

  STATE
    busy
    err_lost_rx_data
    clear_err_lost_rx_data

  DATA
    tx_en ( enable transmission. If disabled, mosi will be 'z', so miso and mosi can be connected )
    tx_valid ( the data on tx_data are valid )
    tx_ready ( ready to receive data. Receiving as soon as tx_valid is 1, the next edge will not be ready anymore)
    tx_data ( the data to transmit )

    rx_en ( reception can be disabled when you want to ignore the data )
    rx_valid ( the data on rx_data are valid )
    rx_confirm ( taking data from rx_data )
    rx_data ( the data to receive. If data aren't received during next word, the communication is stalled! )
    rx_block_on_full ( should rx block communication on full? if not, data can be lost if they are not read in time )

  CONFIGURATION
    en

    clock_polarity
    clock_phase

    size_sel
    div_sel

    pulse_csn

  STRUCTURE
    tx: piso_register
    rx: sipo_register
    ctrl: spi_master_ctrl
    clk_gen: spi_clkgen

spi_slave
  tx: piso_register
  rx: sipo_register
  ctrl: spi_slave_ctrl

spi_dual
  tx: piso_register
  rx: sipo_register
  master_ctrl: spi_master_ctrl
  slave_ctrl: spi_slave_ctrl
  clk_gen: spi_clkgen