library ieee;
use ieee.std_logic_1164.all;

entity dual_port_ram is

  generic (
    SIZE      : natural;
    SIZE_2LOG : natural;
    WIDTH     : natural);

  port (
    wr_clk_i  : in std_logic;
    wr_addr_i : in std_logic_vector(SIZE_2LOG downto 0);
    wr_en_i   : in std_logic;
    wr_data_i : in std_logic_vector(WIDTH - 1 downto 0);

    rd_clk_i  : in  std_logic;
    rd_addr_i : in  std_logic_vector(SIZE_2LOG downto 0);
    rd_data_o : out std_logic_vector(WIDTH - 1 downto 0));

end entity dual_port_ram;

architecture a1 of dual_port_ram is
  type mem_type is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
  signal data : mem_type;
begin  -- architecture a1

  writer: process (wr_clk_i) is
  begin  -- process writer
    if rising_edge(wr_clk_i) then          -- rising clock edge
      if wr_en_i = '1' then
        data(wr_addr_i) <= wr_data_i;
      end if;
    end if;
  end process writer;

  reader: process (rd_clk_i) is
  begin  -- process reader
    if rising_edge(rd_clk_i) then          -- rising clock edge
      rd_data_o <= data(rd_addr_i);
    end if;
  end process reader;

end architecture a1;