library ieee;
use ieee.std_logic_1164.all;

entity counter is

  generic (
    MAX : natural;
    WIDTH : natural);

  port (
    clk_i       : in  std_logic;
    rst_in      : in  std_logic;
    increment_i : in  std_logic;
    count_o     : out std_logic_vector(WIDTH - 1 downto 0));

end entity counter;

architecture a1 of counter is
  signal curr_count : std_logic_vector(WIDTH - 1 downto 0);
  signal next_count : std_logic_vector(WIDTH - 1 downto 0);
begin  -- architecture a1

  set_counter: process (clk_i) is
  begin  -- process set_counter
    if rising_edge(clk_i) then          -- rising clock edge
      if rst_in = '0' then              -- synchronous reset (active low)
        curr_count <= (others => '0');
      else
        curr_count <= next_count;
      end if;
    end if;
  end process set_counter;

  next_count <= curr_count when increment_i = '0' else
                std_logic_vector(unsigned(curr_count) + 1) when curr_count < MAX else
                (others => '0');

  count_o <= curr_count;

end architecture a1;