library ieee;
use ieee.std_logic_1164.all;

entity bin2gray is

  generic (
    WIDTH : natural);

  port (
    bin_i : in std_logic_vector(WIDTH - 1 downto 0);
    gray_o : out std_logic_vector(WIDTH - 1 downto 0));

end entity bin2gray;

architecture a1 of bin2gray is

begin  -- architecture a1

  G(WIDTH - 1) <= bin(WIDTH - 1);
  --generate xor gates.
  xors : for i in 0 to N - 1 generate
      gray_o(i) <= bin_i(i+1) xor bin_i(i);
  end generate xors;

end architecture a1;