This is a simple asynchronous fifo project.
It is meant to be synthesisable, without any
errors in synchronization between the clock domains.

I don't know how to relibaly verify though.
After research I found this article
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
Simulation and Synthesis Techniques for Asynchronous FIFO Design Clifford E. Cummings, Sunburst Design, Inc.,
it looks very good. My fifo is similar to this one, but not the same.
Specifically I decided to make full comparison simpler. I made the fifo SIZE - 1 long
instead of SIZE. While SIZE number of positions in the memory is used, only
SIZE - 1 can be used at single time. This is an unnecessary limitation, but
on the other hand then it seems to me the full conditions is much simpler.
I can just compare the next write address to current read address. When
they match, the fifo is full. Normally there is the problem of distinguishing
between an empty and full state - the fifo is full when pointers match,
but it's also empty when pointers match. It depends on who caught to who.
The article discusses a solution with flipping MSB bit that we add just for
this.

Currently the fifo design is written, but not tested at all not even
in RTL. So I have not yet verified I did not make a silly mistake.