From e2ba9650eff4ff2240afab2514996fe761d6e27d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?= Date: Mon, 12 Jul 2021 15:57:36 +0200 Subject: [PATCH] fix: multiple files synth --- xil/Makefile | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/xil/Makefile b/xil/Makefile index 44e2ff6..dce430b 100644 --- a/xil/Makefile +++ b/xil/Makefile @@ -16,7 +16,7 @@ TOP_ENTITY_BIT_ESCAPED := $(shell echo $(TOP_ENTITY_BIT) | sed "s=\/=\\\/=g") IMPACT_BATCH := impact.cmd IMPACT_BATCH_TEMPLATE := impact.cmd.tmplt -SOURCES_LIST := filelist.txt +PROJECT_FILE := $(shell pwd)/$(TOP_ENTITY).prj .PHONY: all compile flash clean @@ -25,12 +25,12 @@ all: compile flash $(WORKDIR): mkdir $(WORKDIR) -$(SOURCES_LIST): - echo $(SOURCES) | tr " " "\n" > $(SOURCES_LIST) +$(PROJECT_FILE): + echo "$(SOURCES)" | tr " " "\n" | sed -e "s/^/work /" - > $(PROJECT_FILE) -compile: clean $(WORKDIR) $(SOURCES_LIST) +compile: clean $(WORKDIR) $(PROJECT_FILE) cp $(SRCDIR)/*.ucf $(WORKDIR) - $(XFLOW) -p $(DEVICE)-$(PACKAGE) -g srclist:$(SOURCES_LIST) -synth xst_vhdl.opt -implement balanced.opt -config bitgen.opt $(TOP_ENTITY_VHDL) -wd work + $(XFLOW) -p $(DEVICE)-$(PACKAGE) -synth xst_vhdl.opt -implement balanced.opt -config bitgen.opt $(PROJECT_FILE) -wd work $(IMPACT_BATCH): sed -e "s==$(TOP_ENTITY_BIT_ESCAPED)=g" $(IMPACT_BATCH_TEMPLATE) > $(IMPACT_BATCH) @@ -40,6 +40,7 @@ flash: $(IMPACT_BATCH) clean: $(RM) -rf $(WORKDIR) - $(RM) -rf $(SOURCES_LIST) + $(RM) -rf $(PROJECT_FILE) $(RM) -rf $(IMPACT_BATCH) $(RM) -rf _impactbatch.log + $(RM) -rf xflow.his -- 2.48.1