From 7df98a696e44c196dc4bd64ad709a8ad75033e05 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Franti=C5=A1ek=20Boh=C3=A1=C4=8Dek?=
 <fandabohacek@gmail.com>
Date: Sat, 10 Jul 2021 19:23:25 +0200
Subject: [PATCH] feat: add basic template

Template for vhdl application that can be simulated using ghdl.
In xil folder, makefile for Xilinx toolchain can be found (from synthesis to upload to the device)
---
 .gitignore           |  2 ++
 Makefile             | 65 ++++++++++++++++++++++++++++++++++++++++++++
 src/.gitkeep         |  0
 testbench/.gitkeep   |  0
 xil/.gitignore       |  3 ++
 xil/Makefile         | 45 ++++++++++++++++++++++++++++++
 xil/impact.cmd.tmplt |  7 +++++
 7 files changed, 122 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 Makefile
 create mode 100644 src/.gitkeep
 create mode 100644 testbench/.gitkeep
 create mode 100644 xil/.gitignore
 create mode 100644 xil/Makefile
 create mode 100644 xil/impact.cmd.tmplt

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..585ef97
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+_impactbatch.log
+work/
\ No newline at end of file
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..546ed85
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,65 @@
+export ROOT := $(shell pwd)
+SIMDIR := $(ROOT)/sim
+export SRCDIR := $(ROOT)/src
+TBDIR := $(ROOT)/testbench
+WORKDIR := $(ROOT)/work
+
+#####################################################
+#                                                   #
+#                 Top level entity                  #
+#                                                   #
+#####################################################
+export TOP_ENTITY := # fill
+export TOP_ENTITY_VHDL := $(SRCDIR)/$(TOP_ENTITY).$(VHDLEX)
+TESTBENCH ?= $(TOP_ENTITY)_tb # default
+
+WAVEFORM_VIEWER := gtkwave
+
+COMPILER := ghdl
+COMPILER_FLAGS := --workdir=$(WORKDIR)
+VHDLEX := vhd
+
+STOP_TIME ?= 1000ns
+WAVEFORM_FILE ?= $(SIMDIR)/out.gwh
+
+RUN_FLAGS := --stop-time=$(STOP_TIME) --vcd=$(WAVEFORM_FILE) --stats
+
+TBSOURCES := $(wildcard $(TBDIR)/*.$(VHDLEX))
+export SOURCES := $(wildcard $(SRCDIR)/*.$(VHDLEX))
+ALL_SOURCES := $(SOURCES) $(TBSOURCES)
+
+EXECUTABLE := $(SIMDIR)/$(TESTBENCH)
+
+.PHONY: all clean ax309
+
+compile: $(WORKDIR) $(ALL_SOURCES)
+	@$(COMPILER) -i $(COMPILER_FLAGS) $(ALL_SOURCES)
+	@$(COMPILER) -m -o $(EXECUTABLE) $(COMPILER_FLAGS) $(TESTBENCH)
+
+all: compile run view
+
+$(TBDIR)/$(TESTBENCH): compile
+
+$(WORKDIR):
+	@mkdir $(WORKDIR)
+
+$(SIMDIR):
+	@mkdir $(SIMDIR)
+
+run: $(TBDIR)/$(TESTBENCH) $(SIMDIR)
+	@$(EXECUTABLE) $(RUN_FLAGS)
+
+view:
+	@$(WAVEFORM_VIEWER) $(WAVEFORM_FILE)
+
+ax309:
+	@$(MAKE) -C ax309 all
+
+ax309-flash:
+	@$(MAKE) -C ax309 flash
+
+clean:
+	@$(RM) -rf $(SIMDIR)
+	@$(RM) -rf $(WORKDIR)
+	@$(MAKE) -C ax309 clean
+
diff --git a/src/.gitkeep b/src/.gitkeep
new file mode 100644
index 0000000..e69de29
diff --git a/testbench/.gitkeep b/testbench/.gitkeep
new file mode 100644
index 0000000..e69de29
diff --git a/xil/.gitignore b/xil/.gitignore
new file mode 100644
index 0000000..b5b11ff
--- /dev/null
+++ b/xil/.gitignore
@@ -0,0 +1,3 @@
+impact.cmd
+filelist.txt
+work/
diff --git a/xil/Makefile b/xil/Makefile
new file mode 100644
index 0000000..44e2ff6
--- /dev/null
+++ b/xil/Makefile
@@ -0,0 +1,45 @@
+DEVICE := xc6slx9
+PACKAGE := 2ftg256
+
+WORKDIR := ./work
+
+IMPACT := impact
+XFLOW := xflow
+
+# SOURCES is expected to be set to list of files separated by space
+# TOP_ENTITY is expected to be set to top entity's name
+# TOP_ENTITY_VHDL is expected to be set to top entity's vhdl file path
+
+TOP_ENTITY_BIT := $(WORKDIR)/$(TOP_ENTITY).bit
+TOP_ENTITY_BIT_ESCAPED := $(shell echo $(TOP_ENTITY_BIT) | sed "s=\/=\\\/=g")
+
+IMPACT_BATCH := impact.cmd
+IMPACT_BATCH_TEMPLATE := impact.cmd.tmplt
+
+SOURCES_LIST := filelist.txt
+
+.PHONY: all compile flash clean
+
+all: compile flash
+
+$(WORKDIR):
+	mkdir $(WORKDIR)
+
+$(SOURCES_LIST):
+	echo $(SOURCES) | tr " " "\n" > $(SOURCES_LIST)
+
+compile: clean $(WORKDIR) $(SOURCES_LIST)
+	cp $(SRCDIR)/*.ucf $(WORKDIR)
+	$(XFLOW) -p $(DEVICE)-$(PACKAGE) -g srclist:$(SOURCES_LIST) -synth xst_vhdl.opt -implement balanced.opt -config bitgen.opt $(TOP_ENTITY_VHDL) -wd work
+
+$(IMPACT_BATCH):
+	sed -e "s=<bitfile>=$(TOP_ENTITY_BIT_ESCAPED)=g" $(IMPACT_BATCH_TEMPLATE) > $(IMPACT_BATCH)
+
+flash: $(IMPACT_BATCH)
+	$(IMPACT) -batch $(IMPACT_BATCH)
+
+clean:
+	$(RM) -rf $(WORKDIR)
+	$(RM) -rf $(SOURCES_LIST)
+	$(RM) -rf $(IMPACT_BATCH)
+	$(RM) -rf _impactbatch.log
diff --git a/xil/impact.cmd.tmplt b/xil/impact.cmd.tmplt
new file mode 100644
index 0000000..31ff4a0
--- /dev/null
+++ b/xil/impact.cmd.tmplt
@@ -0,0 +1,7 @@
+setMode -bscan
+setcable -p auto
+identify
+
+assignFile -p 1 -file <bitfile>
+program -p 1
+quit
-- 
2.48.1