From c883d63319067c2b820d92e034d94819850496e6 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Thu, 28 Dec 2023 20:34:34 +0100 Subject: [PATCH] fix: compilation errors --- src/i2c/tx.vhd | 8 ++++---- src/utils/delay.vhd | 2 +- src/utils/metastability_filter.vhd | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/i2c/tx.vhd b/src/i2c/tx.vhd index 58dd808..c4d7fef 100644 --- a/src/i2c/tx.vhd +++ b/src/i2c/tx.vhd @@ -76,7 +76,7 @@ architecture a1 of tx is signal ready : std_logic; begin -- architecture a1 - entity utils.delay + scl_falling_delay: entity utils.delay generic map ( DELAY => DELAY_SDA_FOR) port map ( @@ -113,7 +113,7 @@ begin -- architecture a1 if ready = '1' and valid_i = '1' then next_tx_buffers(curr_saving_buffer_index) <= write_data_i; end if; - end process set_next_tx_buffer; + end process set_next_tx_buffers; set_next_buffer_filled: process is begin -- process set_next_buffer_filled @@ -127,7 +127,7 @@ begin -- architecture a1 end if; end process set_next_buffer_filled; - set_next_state: process(curr_state, scl_delayed_pulse, scl_scl, tx_buffer_filled, valid_i) is + set_next_state: process(curr_state, scl_delayed_pulse, curr_scl, tx_buffer_filled, valid_i) is variable start_sending : std_logic := '0'; begin -- process set_next_state next_state <= curr_state; @@ -137,7 +137,7 @@ begin -- architecture a1 next_state <= SENDING; end if; elsif curr_state = SENDING then - if curr_index = 7 and scl_delayed_pulse = '1' then + if curr_bit_index = 7 and scl_delayed_pulse = '1' then next_state <= IDLE; end if; elsif curr_state = WAITING_FOR_DATA then diff --git a/src/utils/delay.vhd b/src/utils/delay.vhd index 3b8380f..2eb7a3c 100644 --- a/src/utils/delay.vhd +++ b/src/utils/delay.vhd @@ -14,7 +14,7 @@ entity delay is end entity delay; architecture a1 of delay is - signal DELAYED_PULSE_POS : natural := DELAY - 1; + constant DELAYED_PULSE_POS : natural := DELAY - 1; signal curr_pulses : std_logic_vector(DELAYED_PULSE_POS downto 0); signal next_pulses : std_logic_vector(DELAYED_PULSE_POS downto 0); begin -- architecture a1 diff --git a/src/utils/metastability_filter.vhd b/src/utils/metastability_filter.vhd index cb50771..02382f3 100644 --- a/src/utils/metastability_filter.vhd +++ b/src/utils/metastability_filter.vhd @@ -14,7 +14,7 @@ architecture a1 of metastability_filter is begin -- architecture a1 - entity work.delay + delay: entity work.delay generic map ( DELAY => 2) port map ( -- 2.48.1