3 files changed, 15 insertions(+), 3 deletions(-)

M src/mcu_slave/counter.vhd
M src/mcu_slave/regs.vhd
M tb/mcu_slave/counter_tb.vhd

@@ 8,6 8,7 @@ library i2c;
 entity counter is
 
   generic (
+    DELAY : integer := 15;
     MAX : integer := 100);
 
   port (


@@ 50,7 51,7 @@ begin
 
   i2c_slave: entity i2c.slave
     generic map (
-      SCL_FALLING_DELAY => 15)
+      SCL_FALLING_DELAY => DELAY)
     port map (
       clk_i          => clk_i,
       rst_in         => rst_n,

@@ 6,6 6,8 @@ library utils;
 library i2c;
 
 entity regs is
+  generic (
+    DELAY : integer := 15);
 
   port (
     clk_i  : in std_logic;


@@ 84,7 86,7 @@ begin
 
   i2c_slave: entity i2c.slave
     generic map (
-      SCL_FALLING_DELAY => 15)
+      SCL_FALLING_DELAY => DELAY)
     port map (
       clk_i          => clk_i,
       rst_in         => rst_n,


@@ 140,4 142,4 @@ begin
     end if;
   end process set_regs;
 
-end architecture a1;>
\ No newline at end of file
+end architecture a1;

@@ 28,11 28,16 @@ architecture tb of counter_tb is
   signal rst : std_logic;
 
   signal scl_override, sda_override : std_logic := '0';
+  signal not_scl : std_logic;
 
   signal err_noack          : std_logic;
   signal bus_busy, dev_busy : std_logic;
+
+  signal one : std_logic := '1';
 begin  -- architecture tb
   uut : entity mcu_slave.counter
+    generic map (
+      DELAY => 1)
     port map (
       clk_i       => clk,
       rst_i       => rst,


@@ 46,11 51,15 @@ begin  -- architecture tb
 
   sda <= not sda_override;
   scl <= not scl_override;
+  not_scl <= not scl;
 
   clk <= not clk after CLK_PERIOD / 2;
   rst_n <= '1' after 2 * CLK_PERIOD;
   rst <= not rst_n;
 
+  -- TODO: allow conditions from master...
+  -- sda_stability_check: check_stable(clk, one, scl, not_scl, sda);
+
   main: process is
   begin  -- process main
     wait until rst_n = '1';