From 71c0e52917861140a6b1c730cfa6a87bf0aab0ae Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@proton.me>
Date: Fri, 29 Dec 2023 10:56:23 +0100
Subject: [PATCH] feat: add possibility for 0 delay in delay entity

---
 src/utils/delay.vhd       | 9 +++++++--
 src/utils/pulse_delay.vhd | 0
 2 files changed, 7 insertions(+), 2 deletions(-)
 delete mode 100644 src/utils/pulse_delay.vhd

diff --git a/src/utils/delay.vhd b/src/utils/delay.vhd
index 2eb7a3c..c90fb1f 100644
--- a/src/utils/delay.vhd
+++ b/src/utils/delay.vhd
@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
 
 entity delay is
   generic (
-    DELAY : natural);
+    DELAY : natural range 0 to 31);
 
   port (
     clk_i   : in std_logic;
@@ -19,7 +19,12 @@ architecture a1 of delay is
   signal next_pulses : std_logic_vector(DELAYED_PULSE_POS downto 0);
 begin  -- architecture a1
 
-  signal_o <= curr_pulses(DELAYED_PULSE_POS);
+  zero_delay: if DELAY = 0 generate
+    signal_o <= signal_i;
+  else generate
+    signal_o <= curr_pulses(DELAYED_PULSE_POS);
+  end generate zero_delay;
+
   next_pulses <= curr_pulses(DELAYED_PULSE_POS - 1 downto 1) & signal_i;
 
   set_regs: process (clk_i) is
diff --git a/src/utils/pulse_delay.vhd b/src/utils/pulse_delay.vhd
deleted file mode 100644
index e69de29..0000000
-- 
2.48.1